(no commit message)

diff --git a/openpower/sv/svp_rewrite/svp64/discussion.mdwn b/openpower/sv/svp_rewrite/svp64/discussion.mdwn
index b1d09d62056e8b426be6e4b4496f35edd2523aa4..a400cbd49d3df51e6247d3fa4fc6b56ab02b0dc9 100644 (file)
--- a/openpower/sv/svp_rewrite/svp64/discussion.mdwn
+++ b/openpower/sv/svp_rewrite/svp64/discussion.mdwn
@@ -12,9 +12,9 @@ do not try to jam VL or MAXVL in.  go with the flow of 24 bits spare.
 * 1: select INT or CR predication
 * 3: predicate selection and inversion (QTY 2 for tpred)
 * 4x2 or 3x3: src1/2/3/dest Vector/Scalar reg
-* 3: saturate mode
+* 5: mode
 
-totals: 22 bits (dest elwidth shared)
+totals: 24 bits (dest elwidth shared)
 
 http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001434.html