regs[rd+i*SUBVL] = regs[rs+i]
+# Twin Predication, saturation, swizzle, and elwidth overrides
+
+Note that mv is a twin-predicated operation, and is swizzlable. This implies that from the vec2, vec3 or vec4, 1 to 8 bytes may be selected and re-ordered (XYZW), mixed with 0 and 1 constants, skipped by way of twin predicate pack and unpack, and a huge amount besides.
+
+Also saturation can be applied to individual elements, including the elements within a vec2/3/4.