# LD not VLD!
# op_width: lb=1, lh=2, lw=4, ld=8
op_load(RT, RA, op_width, immed, svctx, update):
- rdv = map_dest_extra(RT); # possible REMAP
- rsv = map_src_extra(RA); # possible REMAP
ps = get_pred_val(FALSE, RA); # predication on src
pd = get_pred_val(FALSE, RT); # ... AND on dest
for (int i = 0, int j = 0; i < VL && j < VL;):
EA = srcbase + offs
# update RA? load from memory
if update: ireg[rsv+i] = EA;
- ireg[rdv+j] <= MEM[EA];
+ ireg[RT+j] <= MEM[EA];
if (!RT.isvec)
break # destination scalar, end now
if (RA.isvec) i++;