RTL for a SOC configured with cache, a RISCV core, ethernet, DRAM support,
and parameterizeable CSRs.
* [Migen Tutorial](http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>)
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+* There is a great guy, Robert Baruch, who has a good [tutorial](https://github.com/RobertBaruch/nmigen-tutorial) on nMigen. He also build an FPGA-proven Motorola 6800 CPU clone with nMigen and put [the code](https://github.com/RobertBaruch/n6800) and [instructional videos](https://www.youtube.com/playlist?list=PLEeZWGE3PwbbjxV7_XnPSR7ouLR2zjktw) online.
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* [Minerva](https://github.com/lambdaconcept/minerva)
An SOC written in Python nMigen DSL