added tests/memories

diff --git a/Makefile b/Makefile
index 61fb5dc49450ba613c17a77c08551ab656197b9e..6d3d7d7c21ecc22aa33d96566e349c88faecc0c9 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -163,6 +163,7 @@ test: $(TARGETS) $(EXTRA_TARGETS)
        cd tests/asicworld && bash run-test.sh
        cd tests/realmath && bash run-test.sh
        cd tests/techmap && bash run-test.sh
+       cd tests/memories && bash run-test.sh
        cd tests/sat && bash run-test.sh
 
 install: $(TARGETS) $(EXTRA_TARGETS)

diff --git a/tests/memories/.gitignore b/tests/memories/.gitignore
new file mode 100644 (file)
index 0000000..90a0983
--- /dev/null
+++ b/tests/memories/.gitignore
@@ -0,0 +1,3 @@
+*.log
+*.out
+*.dmp

diff --git a/tests/memories/amber23_sram_byte_en.v b/tests/memories/amber23_sram_byte_en.v
new file mode 100644 (file)
index 0000000..3554af8
--- /dev/null
+++ b/tests/memories/amber23_sram_byte_en.v
@@ -0,0 +1,84 @@
+//////////////////////////////////////////////////////////////////
+//                                                              //
+//  Generic Library SRAM with per byte write enable             //
+//                                                              //
+//  This file is part of the Amber project                      //
+//  http://www.opencores.org/project,amber                      //
+//                                                              //
+//  Description                                                 //
+//  Configurable depth and width. The DATA_WIDTH must be a      //
+//  multiple of 8.                                              //
+//                                                              //
+//  Author(s):                                                  //
+//      - Conor Santifort, csantifort.amber@gmail.com           //
+//                                                              //
+//////////////////////////////////////////////////////////////////
+//                                                              //
+// Copyright (C) 2010 Authors and OPENCORES.ORG                 //
+//                                                              //
+// This source file may be used and distributed without         //
+// restriction provided that this copyright statement is not    //
+// removed from the file and that any derivative work contains  //
+// the original copyright notice and the associated disclaimer. //
+//                                                              //
+// This source file is free software; you can redistribute it   //
+// and/or modify it under the terms of the GNU Lesser General   //
+// Public License as published by the Free Software Foundation; //
+// either version 2.1 of the License, or (at your option) any   //
+// later version.                                               //
+//                                                              //
+// This source is distributed in the hope that it will be       //
+// useful, but WITHOUT ANY WARRANTY; without even the implied   //
+// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //
+// PURPOSE.  See the GNU Lesser General Public License for more //
+// details.                                                     //
+//                                                              //
+// You should have received a copy of the GNU Lesser General    //
+// Public License along with this source; if not, download it   //
+// from http://www.opencores.org/lgpl.shtml                     //
+//                                                              //
+//////////////////////////////////////////////////////////////////
+
+// expect-wr-ports 1
+// expect-rd-ports 1
+
+module generic_sram_byte_en
+#(
+parameter DATA_WIDTH    = 32,
+parameter ADDRESS_WIDTH = 4
+)
+
+(
+input                           i_clk,
+input      [DATA_WIDTH-1:0]     i_write_data,
+input                           i_write_enable,
+input      [ADDRESS_WIDTH-1:0]  i_address,
+input      [DATA_WIDTH/8-1:0]   i_byte_enable,
+output reg [DATA_WIDTH-1:0]     o_read_data
+    );
+
+reg [DATA_WIDTH-1:0]   mem  [0:2**ADDRESS_WIDTH-1];
+integer i;
+
+always @(posedge i_clk)
+    begin
+    // read
+    o_read_data <= i_write_enable ? {DATA_WIDTH{1'd0}} : mem[i_address];
+
+    // write
+    if (i_write_enable)
+        for (i=0;i<DATA_WIDTH/8;i=i+1)
+            begin
+            mem[i_address][i*8+0] <= i_byte_enable[i] ? i_write_data[i*8+0] : mem[i_address][i*8+0] ;
+            mem[i_address][i*8+1] <= i_byte_enable[i] ? i_write_data[i*8+1] : mem[i_address][i*8+1] ;
+            mem[i_address][i*8+2] <= i_byte_enable[i] ? i_write_data[i*8+2] : mem[i_address][i*8+2] ;
+            mem[i_address][i*8+3] <= i_byte_enable[i] ? i_write_data[i*8+3] : mem[i_address][i*8+3] ;
+            mem[i_address][i*8+4] <= i_byte_enable[i] ? i_write_data[i*8+4] : mem[i_address][i*8+4] ;
+            mem[i_address][i*8+5] <= i_byte_enable[i] ? i_write_data[i*8+5] : mem[i_address][i*8+5] ;
+            mem[i_address][i*8+6] <= i_byte_enable[i] ? i_write_data[i*8+6] : mem[i_address][i*8+6] ;
+            mem[i_address][i*8+7] <= i_byte_enable[i] ? i_write_data[i*8+7] : mem[i_address][i*8+7] ;
+            end
+    end
+
+endmodule
+

diff --git a/tests/memories/run-test.sh b/tests/memories/run-test.sh
new file mode 100755 (executable)
index 0000000..eccd401
--- /dev/null
+++ b/tests/memories/run-test.sh
@@ -0,0 +1,19 @@
+#!/bin/bash
+
+set -e
+bash ../tools/autotest.sh -G *.v
+
+for f in `egrep -l 'expect-(wr|rd)-ports' *.v`; do
+       echo -n "Testing expectations for $f .."
+       ../../yosys -qp "proc; opt; memory -nomap;; dump -outfile ${f%.v}.dmp t:\$mem" $f
+       if grep -q expect-wr-ports $f; then
+               grep -q "parameter \\\\WR_PORTS $(gawk '/expect-wr-ports/ { print $3; }' amber23_sram_byte_en.v)\$" amber23_sram_byte_en.dmp ||
+                               { echo " ERROR: Unexpected number of write ports."; false; }
+       fi
+       if grep -q expect-rd-ports $f; then
+               grep -q "parameter \\\\RD_PORTS $(gawk '/expect-rd-ports/ { print $3; }' amber23_sram_byte_en.v)\$" amber23_sram_byte_en.dmp ||
+                               { echo " ERROR: Unexpected number of read ports."; false; }
+       fi
+       echo " ok."
+done
+

diff --git a/tests/memories/simple_sram_byte_en.v b/tests/memories/simple_sram_byte_en.v
new file mode 100644 (file)
index 0000000..dee1d22
--- /dev/null
+++ b/tests/memories/simple_sram_byte_en.v
@@ -0,0 +1,26 @@
+// expect-wr-ports 1
+// expect-rd-ports 1
+
+module generic_sram_byte_en #(
+       parameter DATA_WIDTH    = 32,
+       parameter ADDRESS_WIDTH = 4
+) (
+       input                           i_clk,
+       input      [DATA_WIDTH-1:0]     i_write_data,
+       input                           i_write_enable,
+       input      [ADDRESS_WIDTH-1:0]  i_address,
+       input      [DATA_WIDTH/8-1:0]   i_byte_enable,
+       output reg [DATA_WIDTH-1:0]     o_read_data
+);
+
+reg [DATA_WIDTH-1:0] mem [0:2**ADDRESS_WIDTH-1];
+integer i;
+
+always @(posedge i_clk) begin
+       for (i=0;i<DATA_WIDTH/8;i=i+1)
+               if (i_write_enable && i_byte_enable[i])
+                       mem[i_address][i*8 +: 8] <= i_write_data[i*8 +: 8];
+       o_read_data <= mem[i_address];
+end
+
+endmodule