i965: Add some clarification of the WECtrl field.

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index f9c12e1555848593bc1c968012cc42e03d22f638..9633c95ff50a8fc7d8e8162fc7736b6e9173ad60 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -501,9 +501,26 @@
 #define BRW_MASK_ENABLE   0
 #define BRW_MASK_DISABLE  1
 
-/* Sandybridge is WECtrl (Write enable control) */
+/** @{
+ *
+ * Gen6 has replaced "mask enable/disable" with WECtrl, which is
+ * effectively the same but much simpler to think about.  Now, there
+ * are two contributors ANDed together to whether channels are
+ * executed: The predication on the instruction, and the channel write
+ * enable.
+ */
+/**
+ * This is the default value.  It means that a channel's write enable is set
+ * if the per-channel IP is pointing at this instruction.
+ */
 #define BRW_WE_NORMAL          0
-#define BRW_WE_KILL_PRED       1
+/**
+ * This is used like BRW_MASK_DISABLE, and causes all channels to have
+ * their write enable set.  Note that predication still contributes to
+ * whether the channel actually gets written.
+ */
+#define BRW_WE_ALL             1
+/** @} */
 
 #define BRW_OPCODE_MOV        1
 #define BRW_OPCODE_SEL        2

diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c b/src/mesa/drivers/dri/i965/brw_disasm.c
index be27f9226c32343ee94c7aab58cb1e20e1410c1c..12b8f2e46787c79b52f3e6765624f2fd66502579 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_disasm.c
+++ b/src/mesa/drivers/dri/i965/brw_disasm.c
@@ -165,8 +165,8 @@ char *accwr[2] = {
 };
 
 char *wectrl[2] = {
-    [0] = "WEnormal",
-    [1] = "WEpredicted"
+    [0] = "WE_normal",
+    [1] = "WE_all"
 };
 
 char *exec_size[8] = {