cpu: cleanup/re-align

diff --git a/litex/soc/cores/cpu/lm32/core.py b/litex/soc/cores/cpu/lm32/core.py
index 47d65fa0aaccaaefa3d345af9de41bd4f1aae453..f41345bbc5ac7384af17e2e900784299596274f3 100644 (file)
--- a/litex/soc/cores/cpu/lm32/core.py
+++ b/litex/soc/cores/cpu/lm32/core.py
@@ -34,8 +34,8 @@ class LM32(CPU):
 
     def __init__(self, platform, variant="standard"):
         assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
-        self.platform = platform
-        self.variant  = variant
+        self.platform  = platform
+        self.variant   = variant
         self.reset     = Signal()
         self.ibus      = i = wishbone.Interface()
         self.dbus      = d = wishbone.Interface()

diff --git a/litex/soc/cores/cpu/minerva/core.py b/litex/soc/cores/cpu/minerva/core.py
index 8bc86829d383c6944dc69bdec43308dee5fd807e..e52731e5d5d0a7446ad66326ef4710c472614831 100644 (file)
--- a/litex/soc/cores/cpu/minerva/core.py
+++ b/litex/soc/cores/cpu/minerva/core.py
@@ -29,8 +29,8 @@ class Minerva(CPU):
 
     def __init__(self, platform, variant="standard"):
         assert variant is "standard", "Unsupported variant %s" % variant
-        self.platform = platform
-        self.variant  = variant
+        self.platform  = platform
+        self.variant   = variant
         self.reset     = Signal()
         self.ibus      = wishbone.Interface()
         self.dbus      = wishbone.Interface()

diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py
index a190cb779f8a499129a50551230c6f1942e61634..0d934c87989801ad6ef2d0d06a93a88eaf4beb1a 100644 (file)
--- a/litex/soc/cores/cpu/picorv32/core.py
+++ b/litex/soc/cores/cpu/picorv32/core.py
@@ -55,8 +55,8 @@ class PicoRV32(CPU):
 
     def __init__(self, platform, variant="standard"):
         assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
-        self.platform = platform
-        self.variant  = variant
+        self.platform  = platform
+        self.variant   = variant
         self.reset     = Signal()
         self.ibus      = i = wishbone.Interface()
         self.dbus      = d = wishbone.Interface()

diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py
index 2c2025ab374dd64971a6405cdf20511c3f7e6d2e..6ec2cc5e1bbfab3463ec1a89d3124849caf35608 100644 (file)
--- a/litex/soc/cores/cpu/rocket/core.py
+++ b/litex/soc/cores/cpu/rocket/core.py
@@ -79,22 +79,22 @@ class RocketRV64(CPU):
     def __init__(self, platform, variant="standard"):
         assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
 
-        self.platform = platform
-        self.variant  = variant
+        self.platform  = platform
+        self.variant   = variant
 
         self.reset     = Signal()
         self.interrupt = Signal(4)
 
-        self.mem_axi  = mem_axi  = axi.AXIInterface(data_width=64, address_width=32, id_width=4)
-        self.mmio_axi = mmio_axi = axi.AXIInterface(data_width=64, address_width=32, id_width=4)
+        self.mem_axi   =  mem_axi = axi.AXIInterface(data_width=64, address_width=32, id_width=4)
+        self.mmio_axi  = mmio_axi = axi.AXIInterface(data_width=64, address_width=32, id_width=4)
 
-        self.mem_wb64  = mem_wb64  = wishbone.Interface(data_width=64, adr_width=29)
+        self.mem_wb64  =  mem_wb64 = wishbone.Interface(data_width=64, adr_width=29)
         self.mmio_wb64 = mmio_wb64 = wishbone.Interface(data_width=64, adr_width=29)
 
-        self.mem_wb32 = mem_wb32 = wishbone.Interface()
+        self.mem_wb32  =  mem_wb32 = wishbone.Interface()
         self.mmio_wb32 = mmio_wb32 = wishbone.Interface()
 
-        self.buses = [mem_wb32, mmio_wb32]
+        self.buses     = [mem_wb32, mmio_wb32]
 
         # # #
 
@@ -210,16 +210,16 @@ class RocketRV64(CPU):
         )
 
         # adapt axi interfaces to wishbone
-        mem_a2w = ResetInserter()(axi.AXI2Wishbone(mem_axi, mem_wb64, base_address=0))
+        mem_a2w  = ResetInserter()(axi.AXI2Wishbone(mem_axi, mem_wb64, base_address=0))
         mmio_a2w = ResetInserter()(axi.AXI2Wishbone(mmio_axi, mmio_wb64, base_address=0))
         # NOTE: AXI2Wishbone FSMs must be reset with the CPU!
         self.comb += [
-            mem_a2w.reset.eq(ResetSignal() | self.reset),
+            mem_a2w.reset.eq( ResetSignal() | self.reset),
             mmio_a2w.reset.eq(ResetSignal() | self.reset),
         ]
 
         # down-convert wishbone from 64 to 32 bit data width
-        mem_dc = wishbone.Converter(mem_wb64, mem_wb32)
+        mem_dc  = wishbone.Converter(mem_wb64, mem_wb32)
         mmio_dc = wishbone.Converter(mmio_wb64, mmio_wb32)
 
         self.submodules += mem_a2w, mem_dc, mmio_a2w, mmio_dc

diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index 2accda028898c4eb2db426058e5459b5ab698a31..c281943e2a6ab16fe1fcb96ec52ce949439c477d 100644 (file)
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -102,11 +102,11 @@ class VexRiscv(CPU, AutoCSR):
         self.platform         = platform
         self.variant          = variant
         self.external_variant = None
-        self.reset      = Signal()
-        self.ibus       = ibus = wishbone.Interface()
-        self.dbus       = dbus = wishbone.Interface()
-        self.buses      = [ibus, dbus]
-        self.interrupt  = Signal(32)
+        self.reset            = Signal()
+        self.ibus             = ibus = wishbone.Interface()
+        self.dbus             = dbus = wishbone.Interface()
+        self.buses            = [ibus, dbus]
+        self.interrupt        = Signal(32)
 
         self.cpu_params = dict(
                 i_clk=ClockSignal(),