i965: Correct the dp_read message descriptor setup on g4x.

It's mostly like gen4 message descriptor setup, except that the sizes
of type/control changed to be like gen5.  Fixes 21 piglit cases on
gm45, including the regressions in bug #32311 from increased VS
constant buffer usage.

diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c b/src/mesa/drivers/dri/i965/brw_disasm.c
index 6b61f7af15d7e4a1addc66373f4d62da22ff0ce1..111cb9974e1d1d17284c541848ad63047fcfbf6c 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_disasm.c
+++ b/src/mesa/drivers/dri/i965/brw_disasm.c
@@ -973,7 +973,7 @@ int brw_disasm (FILE *file, struct brw_instruction *inst, int gen)
                        inst->bits3.dp_render_cache.send_commit_msg,
                        inst->bits3.dp_render_cache.msg_length,
                        inst->bits3.dp_render_cache.response_length);
-           } else if (gen >= 5) {
+           } else if (gen >= 5 /* FINISHME: || is_g4x */) {
                format (file, " (%d, %d, %d)",
                        inst->bits3.dp_read_gen5.binding_table_index,
                        inst->bits3.dp_read_gen5.msg_control,

diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 6d48ca0e46d7b6a8fb7103098212a68c928d5f8b..f8a3044dd0a0b47fc4a87208b722c147e9ed363a 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -536,6 +536,16 @@ brw_set_dp_read_message(struct brw_context *brw,
        insn->bits3.dp_read_gen5.end_of_thread = 0;
        insn->bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_DATAPORT_READ;
        insn->bits2.send_gen5.end_of_thread = 0;
+   } else if (intel->is_g4x) {
+       insn->bits3.dp_read_g4x.binding_table_index = binding_table_index; /*0:7*/
+       insn->bits3.dp_read_g4x.msg_control = msg_control;  /*8:10*/
+       insn->bits3.dp_read_g4x.msg_type = msg_type;  /*11:13*/
+       insn->bits3.dp_read_g4x.target_cache = target_cache;  /*14:15*/
+       insn->bits3.dp_read_g4x.response_length = response_length;  /*16:19*/
+       insn->bits3.dp_read_g4x.msg_length = msg_length;  /*20:23*/
+       insn->bits3.dp_read_g4x.msg_target = BRW_MESSAGE_TARGET_DATAPORT_READ; /*24:27*/
+       insn->bits3.dp_read_g4x.pad1 = 0;
+       insn->bits3.dp_read_g4x.end_of_thread = 0;
    } else {
        insn->bits3.dp_read.binding_table_index = binding_table_index; /*0:7*/
        insn->bits3.dp_read.msg_control = msg_control;  /*8:11*/

diff --git a/src/mesa/drivers/dri/i965/brw_structs.h b/src/mesa/drivers/dri/i965/brw_structs.h
index 461f27048cc1b7e39a9d0d6fbef73b2b04ca15da..8b6646ca513b1310d2e142b5e7c2943261af0d73 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_structs.h
+++ b/src/mesa/drivers/dri/i965/brw_structs.h
@@ -1663,6 +1663,18 @@ struct brw_instruction
         GLuint end_of_thread:1;
       } dp_read;
 
+      struct {
+        GLuint binding_table_index:8;
+        GLuint msg_control:3;
+        GLuint msg_type:3;
+        GLuint target_cache:2;
+        GLuint response_length:4;
+        GLuint msg_length:4;
+        GLuint msg_target:4;
+        GLuint pad1:3;
+        GLuint end_of_thread:1;
+      } dp_read_g4x;
+
       struct {
         GLuint binding_table_index:8;
         GLuint msg_control:3;