UART: use new bank API and event manager

diff --git a/milkymist/uart/__init__.py b/milkymist/uart/__init__.py
index 42f763ca259b8a83757185a33013bd8a2422d8c0..12ad58550922623a3f078ee5208bf07edcf93f1c 100644 (file)
--- a/milkymist/uart/__init__.py
+++ b/milkymist/uart/__init__.py
@@ -1,20 +1,20 @@
 from migen.fhdl.structure import *
 from migen.bank.description import *
+from migen.bank.eventmanager import *
 from migen.bank import csrgen
 
 class UART:
        def __init__(self, address, clk_freq, baud=115200):
-               self._rxtx = rxtx = Register("rxtx", BV(8))
-               divisor = Register("divisor")
-               self._f_divisor = Field(divisor, "divisor", 8) # TODO: 16
-               stat = Register("stat") # TODO: autogenerated event manager
-               self._f_thre = Field(stat, "thre", access_bus=READ_ONLY, access_dev=WRITE_ONLY)
+               self._rxtx = RegisterRaw("rxtx", 8)
+               self._divisor = RegisterField("divisor", 16, reset=int(clk_freq/baud/16))
                
-               self.bank = csrgen.Bank([rxtx, divisor, stat], address=address)
+               self._tx_event = EventSourceLevel()
+               self.events = EventManager(self._tx_event)
+               self.bank = csrgen.Bank([self._rxtx, self._divisor] + self.events.get_registers(),
+                       address=address)
+
                self.tx = Signal(reset=1)
                self.rx = Signal()
-               
-               self.divisor = int(clk_freq/baud/16) # TODO
        
        def get_fragment(self):
                enable16 = Signal()
@@ -25,7 +25,7 @@ class UART:
                sync = [
                        enable16_counter.eq(enable16_counter - 1),
                        If(enable16,
-                               enable16_counter.eq(self.divisor - 1)) # TODO
+                               enable16_counter.eq(self._divisor.field.r - 1))
                ]
                
                tx_reg = Signal(BV(8))
@@ -33,8 +33,8 @@ class UART:
                tx_count16 = Signal(BV(4))
                tx_busy = Signal()
                sync += [
-                       If(self._rxtx.dev_re,
-                               tx_reg.eq(self._rxtx.dev_r),
+                       If(self._rxtx.re,
+                               tx_reg.eq(self._rxtx.r),
                                tx_bitcount.eq(0),
                                tx_count16.eq(1),
                                tx_busy.eq(1),
@@ -55,10 +55,8 @@ class UART:
                                )
                        )
                ]
+               comb.append(self._tx_event.trigger.eq(tx_busy))
                
-               comb += [
-                       self._f_thre.dev_we.eq(1),
-                       self._f_thre.dev_w.eq(~tx_busy)
-               ]
-               
-               return self.bank.get_fragment() + Fragment(comb, sync, pads={self.tx, self.rx})
+               return self.bank.get_fragment() \
+                       + self.events.get_fragment() \
+                       + Fragment(comb, sync, pads={self.tx, self.rx})