radeon_set_context_reg(cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
radeon_set_context_reg(cs, R_028710_SPI_SHADER_Z_FORMAT,
- pipeline->graphics.shader_z_format);
+ ac_get_spi_shader_z_format(ps->info.fs.writes_z,
+ ps->info.fs.writes_stencil,
+ ps->info.fs.writes_sample_mask));
radeon_set_context_reg(cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
if (pipeline->device->physical_device->has_rbplus)
pipeline->graphics.db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
- unsigned shader_z_format =
- ac_get_spi_shader_z_format(ps->info.fs.writes_z,
- ps->info.fs.writes_stencil,
- ps->info.fs.writes_sample_mask);
- pipeline->graphics.shader_z_format = shader_z_format;
-
calculate_vgt_gs_mode(pipeline);
for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {