i965: Rework the extra flushes surrounding occlusion queries.

This removes the CS stall on Ivybridge.

On Sandybridge, the depth stall needs to be preceded by a non-zero
post-sync op, which requires a CS stall, which needs a stall at
scoreboard.  Emit the full workaround.

Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Eric Anholt <eric@anholt.net>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>

diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c b/src/mesa/drivers/dri/i965/brw_queryobj.c
index 1e03d083dac3fe3377f11a3e0ffb07de4f9a7dfa..b39f6441d12cb1bcaf639dd97960d6af06dbf788 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_queryobj.c
+++ b/src/mesa/drivers/dri/i965/brw_queryobj.c
@@ -91,14 +91,11 @@ static void
 write_depth_count(struct intel_context *intel, drm_intel_bo *query_bo, int idx)
 {
    if (intel->gen >= 6) {
-      BEGIN_BATCH(9);
-
-      /* workaround: CS stall required before depth stall. */
-      OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
-      OUT_BATCH(PIPE_CONTROL_CS_STALL);
-      OUT_BATCH(0); /* write address */
-      OUT_BATCH(0); /* write data */
+      /* Emit Sandybridge workaround flush: */
+      if (intel->gen == 6)
+         intel_emit_post_sync_nonzero_flush(intel);
 
+      BEGIN_BATCH(5);
       OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 2));
       OUT_BATCH(PIPE_CONTROL_DEPTH_STALL |
                 PIPE_CONTROL_WRITE_DEPTH_COUNT);