anv: Always enable the data cache

Because we set the needs_data_cache bit from the NIR during compilation,
any time a shader was pulled out of the pipeline cache, we wouldn't set
the bit and the data cache was disabled.  Fortunately, on Gen8+, this
bit is ignored because we always use the ALL section in the L3$ config
instead of separate DC and RO sections.  On Gen7, however, this meant
that we were basically never running with the data cache enabled and our
compute performance was suffering massively because of it.  This commit
improves Geekbench 5 scores on my Haswell GT3 by roughly 330% (no,
that's not a typo).

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3912>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3912>

diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index e6bd5f903f8eecb35838a00e102644daf3ee95d9..ca073dd2370f5cba1bd9653a4c3524d2dee9cb97 100644 (file)
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -668,9 +668,6 @@ anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
 
    nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
 
-   if (nir->info.num_ssbos > 0 || nir->info.num_images > 0)
-      pipeline->needs_data_cache = true;
-
    NIR_PASS_V(nir, brw_nir_lower_image_load_store, compiler->devinfo);
 
    NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_mem_global,
@@ -1813,7 +1810,7 @@ anv_pipeline_setup_l3_config(struct anv_pipeline *pipeline, bool needs_slm)
    const struct gen_device_info *devinfo = &pipeline->device->info;
 
    const struct gen_l3_weights w =
-      gen_get_default_l3_weights(devinfo, pipeline->needs_data_cache, needs_slm);
+      gen_get_default_l3_weights(devinfo, true, needs_slm);
 
    pipeline->urb.l3_config = gen_get_l3_config(devinfo, w);
    pipeline->urb.total_size =
@@ -1873,8 +1870,6 @@ anv_pipeline_init(struct anv_pipeline *pipeline,
       pCreateInfo->pMultisampleState &&
       pCreateInfo->pMultisampleState->sampleShadingEnable;
 
-   pipeline->needs_data_cache = false;
-
    /* When we free the pipeline, we detect stages based on the NULL status
     * of various prog_data pointers.  Make them NULL by default.
     */

diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 665e8cf54f4291e6badf0a8f3b46810975afdc4f..b4d1a85ebe3e9c4b276af4afecda0456eb3b3a1e 100644 (file)
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -3160,8 +3160,6 @@ struct anv_pipeline {
    VkPipelineCreateFlags                        flags;
    struct anv_subpass *                         subpass;
 
-   bool                                         needs_data_cache;
-
    struct anv_shader_bin *                      shaders[MESA_SHADER_STAGES];
 
    uint32_t                                     num_executables;

diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 82c053d91a559cf8586c12c490c199045e2cd069..6e01377c6f418700865132047bed05d3bcdbcff4 100644 (file)
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -2259,8 +2259,6 @@ compute_pipeline_create(
    memset(pipeline->shaders, 0, sizeof(pipeline->shaders));
    pipeline->num_executables = 0;
 
-   pipeline->needs_data_cache = false;
-
    assert(pCreateInfo->stage.stage == VK_SHADER_STAGE_COMPUTE_BIT);
    pipeline->active_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
    ANV_FROM_HANDLE(anv_shader_module, module,  pCreateInfo->stage.module);