Written CLIPDIST outputs are simply disabled in PA_CL_VS_OUT_CNTL.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
for (reg_index = 0; reg_index < 2; reg_index ++) {
LLVMValueRef *args = pos[2 + reg_index];
- if (!(shader->key.vs.ucps_enabled & (1 << reg_index)))
- continue;
-
shader->clip_dist_write |= 0xf << (4 * reg_index);
args[5] =
param_count++;
break;
case TGSI_SEMANTIC_CLIPDIST:
- if (!(si_shader_ctx->shader->key.vs.ucps_enabled &
- (1 << semantic_index)))
- continue;
shader->clip_dist_write |=
0xf << (semantic_index * 4);
target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
/* The mask of "get_unique_index" bits, needed for ES,
* it describes how the ES->GS ring buffer is laid out. */
uint64_t gs_used_inputs;
- unsigned ucps_enabled:2;
unsigned as_es:1;
} vs;
};
struct si_context *sctx = (struct si_context *)ctx;
memset(key, 0, sizeof(*key));
- if ((sel->type == PIPE_SHADER_VERTEX || sel->type == PIPE_SHADER_GEOMETRY) &&
- sctx->queued.named.rasterizer) {
- if (sctx->queued.named.rasterizer->clip_plane_enable & 0xf0)
- key->vs.ucps_enabled |= 0x2;
- if (sctx->queued.named.rasterizer->clip_plane_enable & 0xf)
- key->vs.ucps_enabled |= 0x1;
- }
-
if (sel->type == PIPE_SHADER_VERTEX) {
unsigned i;
if (!sctx->vertex_elements)