tools/litex_sim_new: switch to dynamically allocated ethmac origin

diff --git a/litex/tools/litex_sim_new.py b/litex/tools/litex_sim_new.py
index 7c17482e5f8834a370ee470dd9ae505b17f80055..52cb4f4d00f2dcea6c3f18aff48051a82f7972a7 100755 (executable)
--- a/litex/tools/litex_sim_new.py
+++ b/litex/tools/litex_sim_new.py
@@ -213,7 +213,7 @@ class SimSoC(SoCCore):
                 interface  = "wishbone",
                 endianness = self.cpu.endianness)
             self.submodules.ethmac = ethmac
-            self.bus.add_slave("ethmac", self.ethmac.bus, SoCRegion(origin=0xb0000000, size=0x2000, cached=False))
+            self.bus.add_slave("ethmac", self.ethmac.bus, SoCRegion(size=0x2000, cached=False))
             self.csr.add("ethmac")
             self.irq.add("ethmac")