arch-riscv: Fix disassembling of jalr

The 'jalr' instruction of 'format Jump' should have an immediate as
offset, and the Rd register could not be always omitted. This patch
fixes the problem.

Example output:
  jalr ra, -168(ra)
  jalr zero, 0(ra)
  jalr ra, 0(a5)

Note that this does not apply to the other two instructions of the
same format: 'c.jr' and 'c.jalr'.

Change-Id: Ia656c2e8bfafd243bfec221ac291190a84684929
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33155
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/arch/riscv/isa/formats/standard.isa b/src/arch/riscv/isa/formats/standard.isa
index 11c06aa7ebcad11b76ffca7478ccdd961eef5323..5c756951b564d635acdd21d88e7d4947bbc39ee6 100644 (file)
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -283,10 +283,13 @@ def template JumpExecute {{
     %(class_name)s::generateDisassembly(
             Addr pc, const Loader::SymbolTable *symtab) const
     {
-        std::vector<RegId> indices = {%(regs)s};
         std::stringstream ss;
         ss << mnemonic << ' ';
-        ss << registerName(indices[0]);
+        if (QUADRANT == 0x3)
+            ss << registerName(_destRegIdx[0]) << ", "
+               << imm << "(" << registerName(_srcRegIdx[0]) << ")";
+        else
+            ss << registerName(_srcRegIdx[0]);
         return ss.str();
     }
 }};