nv30: Add separate nv30 state stuff for fb, based on nv40 one, need to use it now

diff --git a/src/gallium/drivers/nv30/Makefile b/src/gallium/drivers/nv30/Makefile
index 3f80fb87c9b422b3ba11cf525ea0eaa5366b1e7b..ec11de76446178713230e6d578d10cba4eb8569a 100644 (file)
--- a/src/gallium/drivers/nv30/Makefile
+++ b/src/gallium/drivers/nv30/Makefile
@@ -14,6 +14,7 @@ DRIVER_SOURCES = \
        nv30_screen.c \
        nv30_state.c \
        nv30_state_emit.c \
+       nv30_state_fb.c \
        nv30_surface.c \
        nv30_vbo.c \
        nv30_vertprog.c

diff --git a/src/gallium/drivers/nv30/nv30_context.h b/src/gallium/drivers/nv30/nv30_context.h
index 333bd4875c61e8cd1871edc38af4cc4d0c957885..9fbe66dc74e0fb6ac4fd9f313f77aadef6cf405a 100644 (file)
--- a/src/gallium/drivers/nv30/nv30_context.h
+++ b/src/gallium/drivers/nv30/nv30_context.h
@@ -76,6 +76,10 @@ enum nv30_state_index {
 #define NV30_NEW_ARRAYS                (1 << 11)
 #define NV30_NEW_UCP           (1 << 12)
 
+struct nv30_state {
+       struct nouveau_stateobj *hw[NV30_STATE_MAX];
+};
+
 struct nv30_context {
        struct pipe_context pipe;
 
@@ -85,6 +89,9 @@ struct nv30_context {
 
        struct draw_context *draw;
 
+       /* HW state derived from pipe states */
+       struct nv30_state state;
+
        uint32_t dirty;
 
        struct nv30_sampler_state *tex_sampler[PIPE_MAX_SAMPLERS];
@@ -93,6 +100,9 @@ struct nv30_context {
        unsigned fp_samplers;
        unsigned vp_samplers;
 
+       /* Context state */
+       struct pipe_framebuffer_state framebuffer;
+
        uint32_t rt_enable;
        struct pipe_buffer *rt[2];
        struct pipe_buffer *zeta;
@@ -132,6 +142,14 @@ nv30_context(struct pipe_context *pipe)
        return (struct nv30_context *)pipe;
 }
 
+struct nv30_state_entry {
+       boolean (*validate)(struct nv30_context *nv30);
+       struct {
+               unsigned pipe;
+               unsigned hw;
+       } dirty;
+};
+
 extern void nv30_init_state_functions(struct nv30_context *nv30);
 extern void nv30_init_surface_functions(struct nv30_context *nv30);
 extern void nv30_init_query_functions(struct nv30_context *nv30);

diff --git a/src/gallium/drivers/nv30/nv30_state_fb.c b/src/gallium/drivers/nv30/nv30_state_fb.c
new file mode 100644 (file)
index 0000000..73c97e2
--- /dev/null
+++ b/src/gallium/drivers/nv30/nv30_state_fb.c
@@ -0,0 +1,151 @@
+#include "nv30_context.h"
+
+static boolean
+nv30_state_framebuffer_validate(struct nv30_context *nv30)
+{
+       struct pipe_framebuffer_state *fb = &nv30->framebuffer;
+       struct pipe_surface *rt[4], *zeta = NULL;
+       uint32_t rt_enable, rt_format;
+       int i, colour_format = 0, zeta_format = 0;
+       struct nouveau_stateobj *so = so_new(64, 10);
+       unsigned rt_flags = NOUVEAU_BO_RDWR | NOUVEAU_BO_VRAM;
+       unsigned w = fb->width;
+       unsigned h = fb->height;
+
+       rt_enable = 0;
+       for (i = 0; i < fb->num_cbufs; i++) {
+               if (colour_format) {
+                       assert(colour_format == fb->cbufs[i]->format);
+               } else {
+                       colour_format = fb->cbufs[i]->format;
+                       rt_enable |= (NV34TCL_RT_ENABLE_COLOR0 << i);
+                       rt[i] = fb->cbufs[i];
+               }
+       }
+
+       if (rt_enable & (NV34TCL_RT_ENABLE_COLOR1 | NV34TCL_RT_ENABLE_COLOR2 |
+                        NV34TCL_RT_ENABLE_COLOR3))
+               rt_enable |= NV34TCL_RT_ENABLE_MRT;
+
+       if (fb->zsbuf) {
+               zeta_format = fb->zsbuf->format;
+               zeta = fb->zsbuf;
+       }
+
+       rt_format = NV34TCL_RT_FORMAT_TYPE_LINEAR;
+
+       switch (colour_format) {
+       case PIPE_FORMAT_A8R8G8B8_UNORM:
+       case 0:
+               rt_format |= NV34TCL_RT_FORMAT_COLOR_A8R8G8B8;
+               break;
+       case PIPE_FORMAT_R5G6B5_UNORM:
+               rt_format |= NV34TCL_RT_FORMAT_COLOR_R5G6B5;
+               break;
+       default:
+               assert(0);
+       }
+
+       switch (zeta_format) {
+       case PIPE_FORMAT_Z16_UNORM:
+               rt_format |= NV34TCL_RT_FORMAT_ZETA_Z16;
+               break;
+       case PIPE_FORMAT_Z24S8_UNORM:
+       case 0:
+               rt_format |= NV34TCL_RT_FORMAT_ZETA_Z24S8;
+               break;
+       default:
+               assert(0);
+       }
+
+       if (rt_enable & NV34TCL_RT_ENABLE_COLOR0) {
+               uint32_t pitch = rt[0]->pitch * rt[0]->cpp;
+               if (zeta) {
+                       pitch |= (zeta->pitch * zeta->cpp)<<16;
+               } else {
+                       pitch |= pitch<<16;
+               }
+
+               so_method(so, nv30->screen->rankine, NV34TCL_DMA_COLOR0, 1);
+               so_reloc (so, rt[0]->buffer, 0, rt_flags | NOUVEAU_BO_OR,
+                         nv30->nvws->channel->vram->handle,
+                         nv30->nvws->channel->gart->handle);
+               so_method(so, nv30->screen->rankine, NV34TCL_COLOR0_PITCH, 2);
+               so_data  (so, pitch);
+               so_reloc (so, rt[0]->buffer, rt[0]->offset, rt_flags |
+                         NOUVEAU_BO_LOW, 0, 0);
+       }
+
+       if (rt_enable & NV34TCL_RT_ENABLE_COLOR1) {
+               so_method(so, nv30->screen->rankine, NV34TCL_DMA_COLOR1, 1);
+               so_reloc (so, rt[1]->buffer, 0, rt_flags | NOUVEAU_BO_OR,
+                         nv30->nvws->channel->vram->handle,
+                         nv30->nvws->channel->gart->handle);
+               so_method(so, nv30->screen->rankine, NV34TCL_COLOR1_OFFSET, 2);
+               so_reloc (so, rt[1]->buffer, rt[1]->offset, rt_flags |
+                         NOUVEAU_BO_LOW, 0, 0);
+               so_data  (so, rt[1]->pitch * rt[1]->cpp);
+       }
+/*
+       if (rt_enable & NV34TCL_RT_ENABLE_COLOR2) {
+               so_method(so, nv30->screen->rankine, NV34TCL_DMA_COLOR2, 1);
+               so_reloc (so, rt[2]->buffer, 0, rt_flags | NOUVEAU_BO_OR,
+                         nv30->nvws->channel->vram->handle,
+                         nv30->nvws->channel->gart->handle);
+               so_method(so, nv30->screen->rankine, NV34TCL_COLOR2_OFFSET, 1);
+               so_reloc (so, rt[2]->buffer, rt[2]->offset, rt_flags |
+                         NOUVEAU_BO_LOW, 0, 0);
+               so_method(so, nv30->screen->rankine, NV34TCL_COLOR2_PITCH, 1);
+               so_data  (so, rt[2]->pitch * rt[2]->cpp);
+       }
+
+       if (rt_enable & NV34TCL_RT_ENABLE_COLOR3) {
+               so_method(so, nv30->screen->rankine, NV34TCL_DMA_COLOR3, 1);
+               so_reloc (so, rt[3]->buffer, 0, rt_flags | NOUVEAU_BO_OR,
+                         nv30->nvws->channel->vram->handle,
+                         nv30->nvws->channel->gart->handle);
+               so_method(so, nv30->screen->rankine, NV34TCL_COLOR3_OFFSET, 1);
+               so_reloc (so, rt[3]->buffer, rt[3]->offset, rt_flags |
+                         NOUVEAU_BO_LOW, 0, 0);
+               so_method(so, nv30->screen->rankine, NV34TCL_COLOR3_PITCH, 1);
+               so_data  (so, rt[3]->pitch * rt[3]->cpp);
+       }
+*/
+       if (zeta_format) {
+               so_method(so, nv30->screen->rankine, NV34TCL_DMA_ZETA, 1);
+               so_reloc (so, zeta->buffer, 0, rt_flags | NOUVEAU_BO_OR,
+                         nv30->nvws->channel->vram->handle,
+                         nv30->nvws->channel->gart->handle);
+               so_method(so, nv30->screen->rankine, NV34TCL_ZETA_OFFSET, 1);
+               so_reloc (so, zeta->buffer, zeta->offset, rt_flags |
+                         NOUVEAU_BO_LOW, 0, 0);
+               /*so_method(so, nv30->screen->rankine, NV34TCL_ZETA_PITCH, 1);
+               so_data  (so, zeta->pitch * zeta->cpp);*/
+       }
+
+       so_method(so, nv30->screen->rankine, NV34TCL_RT_ENABLE, 1);
+       so_data  (so, rt_enable);
+       so_method(so, nv30->screen->rankine, NV34TCL_RT_HORIZ, 3);
+       so_data  (so, (w << 16) | 0);
+       so_data  (so, (h << 16) | 0);
+       so_data  (so, rt_format);
+       so_method(so, nv30->screen->rankine, NV34TCL_VIEWPORT_HORIZ, 2);
+       so_data  (so, (w << 16) | 0);
+       so_data  (so, (h << 16) | 0);
+       so_method(so, nv30->screen->rankine, NV34TCL_VIEWPORT_CLIP_HORIZ(0), 2);
+       so_data  (so, ((w - 1) << 16) | 0);
+       so_data  (so, ((h - 1) << 16) | 0);
+       so_method(so, nv30->screen->rankine, 0x1d88, 1);
+       so_data  (so, (1 << 12) | h);
+
+       so_ref(so, &nv30->state.hw[NV30_STATE_FB]);
+       return TRUE;
+}
+
+struct nv30_state_entry nv30_state_framebuffer = {
+       .validate = nv30_state_framebuffer_validate,
+       .dirty = {
+               .pipe = NV30_NEW_FB,
+               .hw = NV30_STATE_FB
+       }
+};