Small bug fixes for timing LL/SC. Better now but

not necessarily 100% there yet.

src/mem/cache/cache_impl.hh:
    Generate response packet on failed store conditional.
src/mem/packet.hh:
    Clear packet flags when reinitializing.
    (SATISFIED in particular is one we don't want to leave set.)

--HG--
extra : convert_revision : 29207c8a09afcbce43f41c480ad0c1b21d47454f

diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 64f658907bbe0a430f3cef68a412fd99a68a383a..3c47762f6603fd766c6d7ad81f26c229a943101c 100644 (file)
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -232,7 +232,12 @@ Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
         }
     }
 
-    if (!(pkt->flags & SATISFIED)) {
+    if (pkt->flags & SATISFIED) {
+        // happens when a store conditional fails because it missed
+        // the cache completely
+        if (pkt->needsResponse())
+            respond(pkt, curTick+lat);
+    } else {
         missQueue->handleMiss(pkt, size, curTick + hitLatency);
     }
 

diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index 1a0011d8710910c068caca30b7d7ddd4c660076d..cb97dd0366c9ebb8ab9279fed851317cd9dc9a77 100644 (file)
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -310,6 +310,7 @@ class Packet
      *   multiple transactions. */
     void reinitFromRequest() {
         assert(req->validPaddr);
+        flags = 0;
         addr = req->paddr;
         size = req->size;
         time = req->time;