intel/ir: Remove scheduling-based cycle count estimates.

The cycle count estimation logic part of the scheduler is now
redundant with the shader performance modeling pass, and the estimates
can be consolidated into the brw::performance analysis result object
instead of being part of the CFG, which guarantees that the estimates
cannot be accessed without previously calling the
performance_analysis::require() method, which makes sure that the
right analysis pass is executed at the right time if we don't already
have up-to-date cached results.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

diff --git a/src/intel/compiler/brw_cfg.cpp b/src/intel/compiler/brw_cfg.cpp
index 0fd411b1b9484a5953b9b76633f6b592e3eac6e6..fd88586bac703ea96f12ec864a9694c1a43d4cf0 100644 (file)
--- a/src/intel/compiler/brw_cfg.cpp
+++ b/src/intel/compiler/brw_cfg.cpp
@@ -63,7 +63,7 @@ push_stack(exec_list *list, void *mem_ctx, bblock_t *block)
 }
 
 bblock_t::bblock_t(cfg_t *cfg) :
-   cfg(cfg), start_ip(0), end_ip(0), num(0), cycle_count(0)
+   cfg(cfg), start_ip(0), end_ip(0), num(0)
 {
    instructions.make_empty();
    parents.make_empty();
@@ -173,7 +173,6 @@ cfg_t::cfg_t(const backend_shader *s, exec_list *instructions) :
    block_list.make_empty();
    blocks = NULL;
    num_blocks = 0;
-   cycle_count = 0;
 
    bblock_t *cur = NULL;
    int ip = 0;

diff --git a/src/intel/compiler/brw_cfg.h b/src/intel/compiler/brw_cfg.h
index cec1464c69e1e727994bfbaff142e184091413a6..591d9b4dae2533cdcbbf732a4a97d83687b10d66 100644 (file)
--- a/src/intel/compiler/brw_cfg.h
+++ b/src/intel/compiler/brw_cfg.h
@@ -119,8 +119,6 @@ struct bblock_t {
    struct exec_list parents;
    struct exec_list children;
    int num;
-
-   unsigned cycle_count;
 };
 
 static inline struct backend_instruction *
@@ -329,8 +327,6 @@ struct cfg_t {
    struct exec_list block_list;
    struct bblock_t **blocks;
    int num_blocks;
-
-   unsigned cycle_count;
 };
 
 static inline struct bblock_t *

diff --git a/src/intel/compiler/brw_schedule_instructions.cpp b/src/intel/compiler/brw_schedule_instructions.cpp
index 6edafc8bffcfe5d1fa01066a653717c1dd16c875..7a0fb1ac684d3e9eac68035615494529ccedbc71 100644 (file)
--- a/src/intel/compiler/brw_schedule_instructions.cpp
+++ b/src/intel/compiler/brw_schedule_instructions.cpp
@@ -1762,24 +1762,6 @@ instruction_scheduler::schedule_instructions(bblock_t *block)
    }
 
    assert(instructions_to_schedule == 0);
-
-   block->cycle_count = time;
-}
-
-static unsigned get_cycle_count(cfg_t *cfg)
-{
-   unsigned count = 0, multiplier = 1;
-   foreach_block(block, cfg) {
-      if (block->start()->opcode == BRW_OPCODE_DO)
-         multiplier *= 10; /* assume that loops execute ~10 times */
-
-      count += block->cycle_count * multiplier;
-
-      if (block->end()->opcode == BRW_OPCODE_WHILE)
-         multiplier /= 10;
-   }
-
-   return count;
 }
 
 void
@@ -1821,8 +1803,6 @@ instruction_scheduler::run(cfg_t *cfg)
               post_reg_alloc);
       bs->dump_instructions();
    }
-
-   cfg->cycle_count = get_cycle_count(cfg);
 }
 
 void