bios: we can now use -Ot with_rom True on targets to force bios implementation in...

diff --git a/targets/kc705.py b/targets/kc705.py
index ddbe406f7af5ccfa73b8b91a191f0d7d9c49c9a2..54b287717341f9f0a7956205fcd05ae30797d1eb 100644 (file)
--- a/targets/kc705.py
+++ b/targets/kc705.py
@@ -98,15 +98,16 @@ class BaseSoC(SDRAMSoC):
                self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"), memtype="DDR3")
                self.register_sdram_phy(self.ddrphy.dfi, self.ddrphy.phy_settings, sdram_geom, sdram_timing)
 
-               # BIOS is in SPI flash
-               spiflash_pads = platform.request("spiflash")
-               spiflash_pads.clk = Signal()
-               self.specials += Instance("STARTUPE2",
-                       i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0,
-                       i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
-               self.submodules.spiflash = spiflash.SpiFlash(spiflash_pads, dummy=11, div=2)
-               self.flash_boot_address = 0xb00000
-               self.register_rom(self.spiflash.bus)
+               # If not in ROM, BIOS is in SPI flash
+               if not self.with_rom:
+                       spiflash_pads = platform.request("spiflash")
+                       spiflash_pads.clk = Signal()
+                       self.specials += Instance("STARTUPE2",
+                               i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0,
+                               i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
+                       self.submodules.spiflash = spiflash.SpiFlash(spiflash_pads, dummy=11, div=2)
+                       self.flash_boot_address = 0xb00000
+                       self.register_rom(self.spiflash.bus)
 
 class MiniSoC(BaseSoC):
        csr_map = {

diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py
index a6dab0a6f21e24b6f20bd9bab43f234b7a05aaa4..664caafd2e14190a4d8e284a00f28c35b90dc774 100644 (file)
--- a/targets/mlabs_video.py
+++ b/targets/mlabs_video.py
@@ -54,10 +54,12 @@ class BaseSoC(SDRAMSoC):
                        rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1")
                self.register_sdram_phy(self.ddrphy.dfi, self.ddrphy.phy_settings, sdram_geom, sdram_timing)
 
-               self.submodules.norflash = norflash16.NorFlash16(platform.request("norflash"),
-                       self.ns(110), self.ns(50))
-               self.flash_boot_address = 0x001a0000
-               self.register_rom(self.norflash.bus)
+               # If not in ROM, BIOS is in // NOR flash
+               if not self.with_rom:
+                       self.submodules.norflash = norflash16.NorFlash16(platform.request("norflash"),
+                               self.ns(110), self.ns(50))
+                       self.flash_boot_address = 0x001a0000
+                       self.register_rom(self.norflash.bus)
 
                self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq)
                self.comb += [

diff --git a/targets/pipistrello.py b/targets/pipistrello.py
index 4d7673ec2374990c9934ccbde886e885af2b24cd..a259083a4fe0af0109f84e85f3d58ace41b77dff 100644 (file)
--- a/targets/pipistrello.py
+++ b/targets/pipistrello.py
@@ -97,9 +97,10 @@ class BaseSoC(SDRAMSoC):
                self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"))
                self.register_sdram_phy(self.sdrphy.dfi, self.sdrphy.phy_settings, sdram_geom, sdram_timing)
 
-               # BIOS is in SPI flash
-               self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), dummy=4, div=6)
-               self.flash_boot_address = 0x70000
-               self.register_rom(self.spiflash.bus)
+               # If not in ROM, BIOS is in SPI flash
+               if not self.with_rom:
+                       self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), dummy=4, div=6)
+                       self.flash_boot_address = 0x70000
+                       self.register_rom(self.spiflash.bus)
 
 default_subtarget = BaseSoC

diff --git a/targets/ppro.py b/targets/ppro.py
index a6f59d32c29890459ea2a32d203bef4d978b3e53..d9b1dad89f0ad691bcb3a7c28f4708c1ea6895d5 100644 (file)
--- a/targets/ppro.py
+++ b/targets/ppro.py
@@ -91,9 +91,10 @@ class BaseSoC(SDRAMSoC):
                self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"))
                self.register_sdram_phy(self.sdrphy.dfi, self.sdrphy.phy_settings, sdram_geom, sdram_timing)
 
-               # BIOS is in SPI flash
-               self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), dummy=4, div=6)
-               self.flash_boot_address = 0x70000
-               self.register_rom(self.spiflash.bus)
+               # If not in ROM, BIOS is in SPI flash
+               if not self.with_rom:
+                       self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), dummy=4, div=6)
+                       self.flash_boot_address = 0x70000
+                       self.register_rom(self.spiflash.bus)
 
 default_subtarget = BaseSoC