link: fix rx path

diff --git a/lib/sata/link/__init__.py b/lib/sata/link/__init__.py
index 3941c1fbd605a5c8d5497a6ebe88ed5014812d01..1a5fbfc79d6601de071c3af6f6c056629767db64 100644 (file)
--- a/lib/sata/link/__init__.py
+++ b/lib/sata/link/__init__.py
@@ -135,32 +135,32 @@ class SATALinkRX(Module):
                self.crc = crc = SATACRCChecker(link_description(32))
 
                sop = Signal()
+               eop = Signal()
                self.sync += \
-                       If(fsm.ongoing("RDY"),
-                               sop.eq(1)
-                       ).Elif(scrambler.sink.stb & scrambler.sink.ack,
-                               sop.eq(0)
+                       If(fsm.ongoing("IDLE"),
+                               sop.eq(1),
+                       ).Elif(fsm.ongoing("COPY"),
+                               If(scrambler.sink.stb & scrambler.sink.ack,
+                                       sop.eq(0)
+                               )
                        )
+               self.comb += eop.eq(det == primitives["EOF"])
 
                # small fifo to manage HOLD
                self.fifo = SyncFIFO(link_description(32), 32)
 
                # graph
-               self.sync += \
-                       If(fsm.ongoing("COPY") & (det == 0),
-                               scrambler.sink.stb.eq(cont.source.stb & (cont.source.charisk == 0)),
-                               scrambler.sink.d.eq(cont.source.data),
-                       ).Else(
-                               scrambler.sink.stb.eq(0)
-                       )
                self.comb += [
-                       scrambler.sink.sop.eq(sop),
-                       scrambler.sink.eop.eq(det == primitives["EOF"]),
                        cont.source.ack.eq(1),
                        Record.connect(scrambler.source, crc.sink),
                        Record.connect(crc.source, self.fifo.sink),
                        Record.connect(self.fifo.source, self.source)
                ]
+               cont_source_data_d = Signal(32)
+               self.sync += \
+                       If(cont.source.stb,
+                               scrambler.sink.d.eq(cont.source.data)
+                       )
 
                # FSM
                fsm.act("IDLE",
@@ -172,10 +172,19 @@ class SATALinkRX(Module):
                fsm.act("RDY",
                        insert.eq(primitives["R_RDY"]),
                        If(det == primitives["SOF"],
+                               NextState("WAIT_FIRST")
+                       )
+               )
+               fsm.act("WAIT_FIRST",
+                       insert.eq(primitives["R_IP"]),
+                       If(cont.source.stb,
                                NextState("COPY")
                        )
                )
                fsm.act("COPY",
+                       scrambler.sink.stb.eq(cont.source.stb),
+                       scrambler.sink.sop.eq(sop),
+                       scrambler.sink.eop.eq(eop),
                        insert.eq(primitives["R_IP"]),
                        If(det == primitives["HOLD"],
                                insert.eq(primitives["HOLDA"])
@@ -191,6 +200,7 @@ class SATALinkRX(Module):
                        )
                )
                fsm.act("WTRM",
+                       # XXX: check CRC resutlt to return R_ERR or R_OK
                        insert.eq(primitives["R_OK"]),
                        If(det == primitives["SYNC"],
                                NextState("IDLE")

diff --git a/targets/test.py b/targets/test.py
index 1eaf65f639fa1a91bac6bec36e0d181a175ed7a6..e32de9033aec9b1a2d9a5ede53e86a302818c5b6 100644 (file)
--- a/targets/test.py
+++ b/targets/test.py
@@ -312,16 +312,44 @@ class TestDesign(UART2WB, AutoCSR):
                        self.sata_con.sink.read,
                        self.sata_con.sink.identify,
 
-                       self.sata_con.source.stb,
-                       self.sata_con.source.sop,
-                       self.sata_con.source.eop,
-                       self.sata_con.source.ack,
-                       self.sata_con.source.write,
-                       self.sata_con.source.read,
-                       self.sata_con.source.identify,
-                       self.sata_con.source.success,
-                       self.sata_con.source.failed,
-                       self.sata_con.source.data,
+                       #self.sata_con.source.stb,
+                       #self.sata_con.source.sop,
+                       #self.sata_con.source.eop,
+                       #self.sata_con.source.ack,
+                       #self.sata_con.source.write,
+                       #self.sata_con.source.read,
+                       #self.sata_con.source.identify,
+                       #self.sata_con.source.success,
+                       #self.sata_con.source.failed,
+                       #self.sata_con.source.data,
+
+                       #self.sata_con.link.source.stb,
+                       #self.sata_con.link.source.sop,
+                       #self.sata_con.link.source.eop,
+                       #self.sata_con.link.source.ack,
+                       #self.sata_con.link.source.d,
+                       #self.sata_con.link.source.error,
+
+                       #self.sata_con.link.rx.scrambler.sink.stb,
+                       #self.sata_con.link.rx.scrambler.sink.sop,
+                       #self.sata_con.link.rx.scrambler.sink.eop,
+                       #self.sata_con.link.rx.scrambler.sink.ack,
+                       #self.sata_con.link.rx.scrambler.sink.d,
+                       #self.sata_con.link.rx.scrambler.sink.error,
+
+                       self.sata_con.link.rx.scrambler.sink.stb,
+                       self.sata_con.link.rx.scrambler.sink.sop,
+                       self.sata_con.link.rx.scrambler.sink.eop,
+                       self.sata_con.link.rx.scrambler.sink.ack,
+                       self.sata_con.link.rx.scrambler.sink.d,
+                       self.sata_con.link.rx.scrambler.sink.error,
+
+                       self.sata_con.link.rx.scrambler.source.stb,
+                       self.sata_con.link.rx.scrambler.source.sop,
+                       self.sata_con.link.rx.scrambler.source.eop,
+                       self.sata_con.link.rx.scrambler.source.ack,
+                       self.sata_con.link.rx.scrambler.source.d,
+                       self.sata_con.link.rx.scrambler.source.error,
 
                        self.command_tx_fsm_state,
                        self.transport_tx_fsm_state,