projects
/
openpower-isa.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
| inline |
side by side
(parent:
e4a4492
)
take deepcopy of regs passed in to avoid accidental modification
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Tue, 5 Jul 2022 13:02:29 +0000
(14:02 +0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Tue, 5 Jul 2022 13:02:29 +0000
(14:02 +0100)
src/openpower/test/state.py
patch
|
blob
|
history
diff --git
a/src/openpower/test/state.py
b/src/openpower/test/state.py
index ee884f81e4e32d10f0f43137e9c055ba52e8d860..f8eae6485240a0ebfbf8b0f12c0d14ad108de01f 100644
(file)
--- a/
src/openpower/test/state.py
+++ b/
src/openpower/test/state.py
@@
-27,6
+27,7
@@
from openpower.decoder.isa.radixmmu import RADIX
from openpower.util import log
import os
import sys
+from copy import deepcopy
global staterunner_factory
staterunner_factory = {}
@@
-242,13
+243,13
@@
class ExpectedState(State):
int_regs = 32
if isinstance(int_regs, int):
int_regs = [0] * int_regs
- self.intregs =
int_regs
+ self.intregs =
deepcopy(int_regs)
self.pc = pc
if crregs is None:
crregs = 8
if isinstance(crregs, int):
crregs = [0] * crregs
- self.crregs =
crregs
+ self.crregs =
deepcopy(crregs)
self.so = so
self.ov = ov
self.ca = ca