clarify intro

diff --git a/3d_gpu.mdwn b/3d_gpu.mdwn
index 42af75d88e32826a5f94d2b4e24e50fd6f554593..6f51ab40cd47fe2fdd87cd75f1405a4f7d76fe54 100644 (file)
--- a/3d_gpu.mdwn
+++ b/3d_gpu.mdwn
@@ -7,17 +7,20 @@ Our primary goal is to design a **complete** all-in-one processor
 (System-on-a-Chip) that happens to include a libre-licensed VPU and GPU.
 
 We seek investors, sponsors, engineers and potential customers, who are
-interested in the creation and use of an entirely libre low-power mobile
-class system-on-a-chip.  Comparative benchmark performance, pincount and
-price is the Allwinner A64, except that the power budget target is 2.5 watts
-in a 16x16mm 320 to 360 pin 0.8mm FBGA package.
+interested, as a first product, in the creation and use of an entirely
+libre low-power mobile class system-on-a-chip.  Comparative benchmark
+performance, pincount and price is the Allwinner A64, except that the
+power budget target is 2.5 watts in a 16x16mm 320 to 360 pin 0.8mm
+FBGA package.  Instead of single-issue higher clock rate, the design is
+multi-issue, aiming for around 800mhz.
 
 The lower pincount, lower power, and higher BGA pitch is all to reduce
 the cost of product development when it comes to PCB design and layout:
 
-* Above 4 watts requires metal packages, thermal management and much
-  pricier PMICs.
-* 0.6mm pitch BGA and below requires much more expensive PCBA techniques.
+* Above 4 watts requires metal packages, greater attention to thermal
+  management in the PCB design and layout, and much pricier PMICs.
+* 0.6mm pitch BGA and below requires much more expensive PCB manufacturing
+  equipment and more costly PCBA techniques.
 * Above 600 pins begins to reduce production yields as well as increase
   the cost of testing and packaging.