i965: Extend is_haswell checks to gen >= 8 in Gen4-7 generators.

We're going to use fs_generator/vec4_generator for Gen8+ code soon,
thanks to the new brw_instruction API.  When we do, we'll generally
want to take the Haswell paths on Gen8+ as well.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index ce1b823fcc2a8458a161ad71e574efcea8fc6f74..9b39261930b835f67a1877da497ed9ad88d3852f 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -421,7 +421,7 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src
       case SHADER_OPCODE_TXD:
          if (inst->shadow_compare) {
             /* Gen7.5+.  Otherwise, lowered by brw_lower_texture_gradients(). */
-            assert(brw->is_haswell);
+            assert(brw->gen >= 8 || brw->is_haswell);
             msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
          } else {
             msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
@@ -578,7 +578,7 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src
              * offset, and each sampler state is only 16-bytes, so we can't
              * exclusively use the offset - we have to use both.
              */
-            assert(brw->is_haswell); /* field only exists on Haswell */
+            assert(brw->gen >= 8 || brw->is_haswell);
             brw_ADD(p,
                     get_element_ud(header_reg, 3),
                     get_element_ud(brw_vec8_grf(0, 0), 3),
@@ -1384,7 +1384,7 @@ fs_generator::generate_code(exec_list *instructions)
       case BRW_OPCODE_MAD:
          assert(brw->gen >= 6);
         brw_set_default_access_mode(p, BRW_ALIGN_16);
-         if (dispatch_width == 16 && !brw->is_haswell) {
+         if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
            brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
            brw_MAD(p, dst, src[0], src[1], src[2]);
            brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
@@ -1399,7 +1399,7 @@ fs_generator::generate_code(exec_list *instructions)
       case BRW_OPCODE_LRP:
          assert(brw->gen >= 6);
         brw_set_default_access_mode(p, BRW_ALIGN_16);
-         if (dispatch_width == 16 && !brw->is_haswell) {
+         if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
            brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
            brw_LRP(p, dst, src[0], src[1], src[2]);
            brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
@@ -1495,7 +1495,7 @@ fs_generator::generate_code(exec_list *instructions)
       case BRW_OPCODE_BFE:
          assert(brw->gen >= 7);
          brw_set_default_access_mode(p, BRW_ALIGN_16);
-         if (dispatch_width == 16 && !brw->is_haswell) {
+         if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
             brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
             brw_BFE(p, dst, src[0], src[1], src[2]);
             brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index aa041bc613aaf5f83255290b067fe121c853df70..f6eb3d4356045b16e6959c57951e2988ba6a955d 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -248,7 +248,7 @@ vec4_generator::generate_tex(vec4_instruction *inst,
       case SHADER_OPCODE_TXD:
          if (inst->shadow_compare) {
             /* Gen7.5+.  Otherwise, lowered by brw_lower_texture_gradients(). */
-            assert(brw->is_haswell);
+            assert(brw->gen >= 8 || brw->is_haswell);
             msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
          } else {
             msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
@@ -355,7 +355,7 @@ vec4_generator::generate_tex(vec4_instruction *inst,
              * offset, and each sampler state is only 16-bytes, so we can't
              * exclusively use the offset - we have to use both.
              */
-            assert(brw->is_haswell); /* field only exists on Haswell */
+            assert(brw->gen >= 8 || brw->is_haswell);
             brw_ADD(p,
                     get_element_ud(header, 3),
                     get_element_ud(brw_vec8_grf(0, 0), 3),