+2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
+
+ * bfd-in.h (elf_internal_abiflags_v0): New struct declaration.
+ (bfd_mips_elf_get_abiflags): New prototype.
+ * elfxx-mips.c (bfd_mips_elf_get_abiflags): New function.
+ * bfd-in2.h: Regenerate.
+
2016-12-14 Yury Norov <ynorov@caviumnetworks.com>
* bfd/elfnn-aarch64.c: fix TLS relaxations for ilp32 where
extern bfd_boolean v850_elf_set_note
(bfd *, unsigned int, unsigned int);
+
+/* MIPS ABI flags data access. For the disassembler. */
+struct elf_internal_abiflags_v0;
+extern struct elf_internal_abiflags_v0 *bfd_mips_elf_get_abiflags (bfd *);
extern bfd_boolean v850_elf_set_note
(bfd *, unsigned int, unsigned int);
+
+/* MIPS ABI flags data access. For the disassembler. */
+struct elf_internal_abiflags_v0;
+extern struct elf_internal_abiflags_v0 *bfd_mips_elf_get_abiflags (bfd *);
/* Extracted from init.c. */
void bfd_init (void);
return n;
}
+/* Return the ABI flags associated with ABFD if available. */
+
+Elf_Internal_ABIFlags_v0 *
+bfd_mips_elf_get_abiflags (bfd *abfd)
+{
+ struct mips_elf_obj_tdata *tdata = mips_elf_tdata (abfd);
+
+ return tdata->abiflags_valid ? &tdata->abiflags : NULL;
+}
+
void
_bfd_mips_post_process_headers (bfd *abfd, struct bfd_link_info *link_info)
{
+2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
+
+ * testsuite/binutils-all/mips/mips-ase-1.d: New test.
+ * testsuite/binutils-all/mips/mips-ase-2.d: New test.
+ * testsuite/binutils-all/mips/mips-ase-3.d: New test.
+ * testsuite/binutils-all/mips/mips-ase-1.s: New test source.
+ * testsuite/binutils-all/mips/mips-ase-2.s: New test source.
+ * testsuite/binutils-all/mips/mips.exp: Run the new tests.
+
2016-12-13 Jiong Wang <jiong.wang@arm.com>
* readelf.c (is_32bit_abs_reloc): Recognize R_AARCH64_P32_ABS32.
--- /dev/null
+#PROG: objcopy
+#objdump: -dp --prefix-addresses --show-raw-insn
+#name: MIPS ELF file ASE information interpretation for disassembly 1
+#as: -32
+
+# Verify that in the absence of its ASE flag MDMX code is not disassembled
+# with MIPS64r2, where MDMX presence is not implied.
+
+.*: +file format .*mips.*
+!private flags = .*mdmx.*
+
+MIPS ABI Flags Version: 0
+
+ISA: MIPS64r2
+GPR size: 32
+CPR1 size: 64
+CPR2 size: 0
+FP ABI: Hard float \(32-bit CPU, 64-bit FPU\)
+ISA Extension: None
+ASEs:
+ None
+FLAGS 1: .*
+FLAGS 2: .*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 7aa2080b 0x7aa2080b
+[0-9a-f]+ <[^>]*> 46c520c0 add\.ps \$f3,\$f4,\$f5
+[0-9a-f]+ <[^>]*> 46c83998 addr\.ps \$f6,\$f7,\$f8
+ \.\.\.
--- /dev/null
+ .module mips64r2
+ .module fp=64
+ .set mdmx
+ .set mips3d
+foo:
+ add.qh $v0, $v1, $v2
+ add.ps $f3, $f4, $f5
+ addr.ps $f6, $f7, $f8
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
--- /dev/null
+#PROG: objcopy
+#objdump: -dp --prefix-addresses --show-raw-insn
+#name: MIPS ELF file ASE information interpretation for disassembly 2
+#as: -32
+
+# Verify that in the presence of its ASE flag MDMX code is disassembled
+# with MIPS64r2, where MDMX presence is not implied.
+
+.*: +file format .*mips.*
+private flags = .[8-f]......: .*mdmx.*
+
+MIPS ABI Flags Version: 0
+
+ISA: MIPS64r2
+GPR size: 32
+CPR1 size: 64
+CPR2 size: 0
+FP ABI: Hard float \(32-bit CPU, 64-bit FPU\)
+ISA Extension: None
+ASEs:
+ MDMX ASE
+FLAGS 1: .*
+FLAGS 2: .*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 7aa2080b add\.qh \$v0,\$v1,\$v2
+[0-9a-f]+ <[^>]*> 46c520c0 add\.ps \$f3,\$f4,\$f5
+[0-9a-f]+ <[^>]*> 46c83998 addr\.ps \$f6,\$f7,\$f8
+ \.\.\.
--- /dev/null
+ .module mips64r2
+ .module fp=64
+ .module mdmx
+ .set mips3d
+foo:
+ add.qh $v0, $v1, $v2
+ add.ps $f3, $f4, $f5
+ addr.ps $f6, $f7, $f8
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
--- /dev/null
+#PROG: objcopy
+#objdump: -dp --prefix-addresses --show-raw-insn
+#name: MIPS ELF file ASE information interpretation for disassembly 3
+#as: -32
+#objcopy: -R .MIPS.abiflags
+#source: mips-ase-2.s
+
+# Verify that in the presence of its ASE flag MDMX code is disassembled
+# with MIPS64r2, where MDMX presence is not implied.
+
+.*: +file format .*mips.*
+private flags = .[8-f]......: .*mdmx.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 7aa2080b add\.qh \$v0,\$v1,\$v2
+[0-9a-f]+ <[^>]*> 46c520c0 add\.ps \$f3,\$f4,\$f5
+[0-9a-f]+ <[^>]*> 46c83998 addr\.ps \$f6,\$f7,\$f8
+ \.\.\.
}
if [is_elf_format] {
+ run_dump_test "mips-ase-1"
+ run_dump_test "mips-ase-2"
+ run_dump_test "mips-ase-3"
run_dump_test "mixed-mips16"
run_dump_test "mixed-micromips"
run_dump_test "mixed-mips16-micromips"
+2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
+
+ * elf/mips.h (Elf_Internal_ABIFlags_v0): Also declare struct
+ typedef as `elf_internal_abiflags_v0'.
+
2016-12-13 Renlin Li <renlin.li@arm.com>
* opcode/aarch64.h (aarch64_operand_class): Remove
unsigned char flags2[4];
} Elf_External_ABIFlags_v0;
-typedef struct
+typedef struct elf_internal_abiflags_v0
{
/* Version of flags structure. */
unsigned short version;
+2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips-dis.c (mips_convert_abiflags_ases): New function.
+ (set_default_mips_dis_options): Also infer ASE flags from ELF
+ file structures.
+
2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
* mips-dis.c (set_default_mips_dis_options): Reorder ELF file
return 0;
}
+/* Convert ASE flags from .MIPS.abiflags to internal values. */
+
+static unsigned long
+mips_convert_abiflags_ases (unsigned long afl_ases)
+{
+ unsigned long opcode_ases = 0;
+
+ if (afl_ases & AFL_ASE_DSP)
+ opcode_ases |= ASE_DSP;
+ if (afl_ases & AFL_ASE_DSPR2)
+ opcode_ases |= ASE_DSPR2;
+ if (afl_ases & AFL_ASE_EVA)
+ opcode_ases |= ASE_EVA;
+ if (afl_ases & AFL_ASE_MCU)
+ opcode_ases |= ASE_MCU;
+ if (afl_ases & AFL_ASE_MDMX)
+ opcode_ases |= ASE_MDMX;
+ if (afl_ases & AFL_ASE_MIPS3D)
+ opcode_ases |= ASE_MIPS3D;
+ if (afl_ases & AFL_ASE_MT)
+ opcode_ases |= ASE_MT;
+ if (afl_ases & AFL_ASE_SMARTMIPS)
+ opcode_ases |= ASE_SMARTMIPS;
+ if (afl_ases & AFL_ASE_VIRT)
+ opcode_ases |= ASE_VIRT;
+ if (afl_ases & AFL_ASE_MSA)
+ opcode_ases |= ASE_MSA;
+ if (afl_ases & AFL_ASE_XPA)
+ opcode_ases |= ASE_XPA;
+ if (afl_ases & AFL_ASE_DSPR3)
+ opcode_ases |= ASE_DSPR3;
+ return opcode_ases;
+}
+
static void
set_default_mips_dis_options (struct disassemble_info *info)
{
/* Update settings according to the ELF file header flags. */
if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
{
- Elf_Internal_Ehdr *header;
+ struct bfd *abfd = info->section->owner;
+ Elf_Internal_Ehdr *header = elf_elfheader (abfd);
+ Elf_Internal_ABIFlags_v0 *abiflags = bfd_mips_elf_get_abiflags (abfd);
- header = elf_elfheader (info->section->owner);
/* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
if (is_newabi (header))
mips_gpr_names = mips_gpr_names_newabi;
/* If a microMIPS binary, then don't use MIPS16 bindings. */
micromips_ase = is_micromips (header);
+ /* OR in any extra ASE flags set in ELF file structures. */
+ if (abiflags)
+ mips_ase |= mips_convert_abiflags_ases (abiflags->ases);
+ else if (header->e_flags & EF_MIPS_ARCH_ASE_MDMX)
+ mips_ase |= ASE_MDMX;
}
}
projects / binutils-gdb.git / commitdiff