--- /dev/null
+from migen.fhdl.structure import *
+from migen.fhdl import verilog, autofragment
+from migen.bus import csr
+from migen.bus.transactions import *
+from migen.bank import description, csrgen
+from migen.bank.description import *
+
+import sys
+sys.path.append("../../../")
+
+from migScope import trigger, recorder, migIo
+from migScope.tools.truthtable import *
+from migScope.tools.vcd import *
+import spi2Csr
+from spi2Csr.tools.uart2Spi import *
+
+#==============================================================================
+# P A R A M E T E R S
+#==============================================================================
+# Bus Width
+trig_width = 16
+dat_width = 16
+
+# Record Size
+record_size = 4096
+
+# Csr Addr
+MIGIO0_ADDR = 0x0000
+TRIGGER_ADDR = 0x0200
+RECORDER_ADDR = 0x0400
+
+csr = Uart2Spi(1,115200)
+
+# MigScope Configuration
+# migIo
+migIo0 = migIo.MigIo(MIGIO0_ADDR, 8, "IO",csr)
+
+# Trigger
+term0 = trigger.Term(trig_width)
+trigger0 = trigger.Trigger(TRIGGER_ADDR, trig_width, dat_width, [term0], csr)
+
+# Recorder
+recorder0 = recorder.Recorder(RECORDER_ADDR, dat_width, record_size, csr)
+
+#==============================================================================
+# T E S T M I G L A
+#==============================================================================
+dat_vcd = []
+recorder0.size(1024)
+
+def capture():
+ global trigger0
+ global recorder0
+ global dat_vcd
+ sum_tt = gen_truth_table("term0")
+ trigger0.sum.write(sum_tt)
+ recorder0.reset()
+ recorder0.offset(0)
+ recorder0.arm()
+ print("-Recorder [Armed]")
+ print("-Waiting Trigger...", end = ' ')
+ while(not recorder0.is_done()):
+ time.sleep(0.1)
+ print("[Done]")
+
+ print("-Receiving Data...", end = ' ')
+ sys.stdout.flush()
+ dat_vcd += recorder0.read(1024)
+ print("[Done]")
+
+print("Capturing Ramp..")
+print("----------------------")
+term0.write(0x0000)
+csr.write(0x0000, 0)
+capture()
+
+print("Capturing Square..")
+print("----------------------")
+term0.write(0x0000)
+csr.write(0x0000, 1)
+capture()
+
+print("Capturing Sinus..")
+print("----------------------")
+term0.write(0x0080)
+csr.write(0x0000, 2)
+capture()
+
+myvcd = Vcd()
+myvcd.add(Var("wire", 16, "trig_dat", dat_vcd))
+myvcd.write("test_MigLa.vcd")
\ No newline at end of file
#Write Path
self.put = Signal()
self.put_dat = Signal(BV(self.width))
- self._put_cnt = Signal(BV(self.depth_width))
self._put_ptr = Signal(BV(self.depth_width))
+ self._put_ptr_stop = Signal(BV(self.depth_width))
self._put_port = MemoryPort(adr=self._put_ptr, we=self.put, dat_w=self.put_dat)
#Read Path
self.get = Signal()
self.get_dat = Signal(BV(self.width))
- self._get_cnt = Signal(BV(self.depth_width))
self._get_ptr = Signal(BV(self.depth_width))
self._get_port = MemoryPort(adr=self._get_ptr, re=self.get, dat_r=self.get_dat)
#Others
#Control
sync += [
If(self.rst,
- self._put_cnt.eq(0),
- self._put_ptr.eq(0),
- self.run.eq(0)
+ self.run.eq(0),
+ self._put_ptr.eq(0)
).Elif(self.start & ~self.run,
- self._put_cnt.eq(0),
self.run.eq(1),
- If(self.put,
- self._put_cnt.eq(self._put_cnt+1),
- self._put_ptr.eq(self._put_ptr+1)
- )
+ self._put_ptr_stop.eq(self._put_ptr + self.size - self.offset)
).Elif(self.done,
self.run.eq(0)
- ).Elif(self.put & ~self.done,
- self._put_cnt.eq(self._put_cnt+1),
+ ),
+
+ If(self.put & ~self.done,
self._put_ptr.eq(self._put_ptr+1)
),
+ If(self.rst,
+ self.done.eq(0)
+ ).Elif((self._put_ptr == self._put_ptr_stop) & self.run,
+ self.done.eq(1)
+ ),
If(self.rst,
- self._get_cnt.eq(0),
- self._get_ptr.eq(0),
+ self._get_ptr.eq(0)
).Elif(self.start & ~self.run,
- self._get_cnt.eq(0),
- self._get_ptr.eq(self._put_ptr-self.offset-1),
+ self._get_ptr.eq(self._put_ptr-self.offset-1)
).Elif(self.get,
- self._get_cnt.eq(self._get_cnt+1),
self._get_ptr.eq(self._get_ptr+1)
)
-
- ]
- comb += [
- If((self._put_cnt == size_minus_offset-2) & self.run,
- self.done.eq(1)
- ).Else(
- self.done.eq(0)
- )
]
return Fragment(comb=comb, sync=sync, memories=memories)
def arm(self):
self.interface.write(self.address + 0x01, 1)
+ self.interface.write(self.address + 0x01, 0)
def is_done(self):
return self.interface.read(self.address + 0x02) == 1
projects / litex.git / commitdiff