from misoclib.sdram import dfii
from misoclib.sdram.minicon import Minicon
+def mem_decoder(address, start=26, end=29):
+ return lambda a: a[start:end] == ((address >> (start+2)) & (2**(end-start))-1)
+
class GenSoC(Module):
csr_map = {
"crg": 0, # user
"uart": 0,
"timer0": 1,
}
-
+ mem_map = {
+ "rom": 0x00000000, # (shadow @0x80000000)
+ "sram": 0x10000000, # (shadow @0x90000000)
+ "csr": 0x60000000, # (shadow @0xe0000000)
+ }
def __init__(self, platform, clk_freq, cpu_reset_address, sram_size=4096, l2_size=0, with_uart=True, cpu_type="lm32",
csr_data_width=8, csr_address_width=14):
self.clk_freq = clk_freq
# CSR bridge 0x60000000 (shadow @0xe0000000) provided
self._wb_masters = [self.cpu.ibus, self.cpu.dbus]
self._wb_slaves = [
- (lambda a: a[26:29] == 1, self.sram.bus),
- (lambda a: a[26:29] == 6, self.wishbone2csr.wishbone)
+ (mem_decoder(self.mem_map["sram"]), self.sram.bus),
+ (mem_decoder(self.mem_map["csr"]), self.wishbone2csr.wishbone)
]
- self.add_cpu_memory_region("sram", 0x10000000, sram_size)
+ self.add_cpu_memory_region("sram", self.mem_map["sram"], sram_size)
# CSR
if with_uart:
raise FinalizeError
self._rom_registered = True
- self.add_wb_slave(lambda a: a[26:29] == 0, rom_wb_if)
+ self.add_wb_slave(mem_decoder(self.mem_map["rom"]), rom_wb_if)
self.add_cpu_memory_region("rom", self.cpu_reset_address, bios_size)
def add_wb_master(self, wbm):
data_width=self.csr_data_width, address_width=self.csr_address_width)
self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
- self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), csrs)
+ self.add_cpu_csr_region(name, self.mem_map["csr"]+0x80000000+0x800*mapaddr, flen(rmap.bus.dat_w), csrs)
for name, memory, mapaddr, mmap in self.csrbankarray.srams:
- self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), memory)
+ self.add_cpu_csr_region(name, self.mem_map["csr"]+0x80000000+0x800*mapaddr, flen(rmap.bus.dat_w), memory)
# Interrupts
for k, v in sorted(self.interrupt_map.items(), key=itemgetter(1)):
}
csr_map.update(GenSoC.csr_map)
+ mem_map = {
+ "sdram": 0x40000000, # (shadow @0xc0000000)
+ }
+ mem_map.update(GenSoC.mem_map)
+
def __init__(self, platform, clk_freq, cpu_reset_address, with_memtest=False, sram_size=4096, l2_size=8192, with_uart=True, ramcon_type="lasmicon", **kwargs):
GenSoC.__init__(self, platform, clk_freq, cpu_reset_address, sram_size, l2_size, with_uart, **kwargs)
self.with_memtest = with_memtest
phy_settings.dfi_d, phy_settings.nphases)
self.submodules.dficon0 = dfi.Interconnect(self.dfii.master, phy_dfi)
+ # LASMICON
if self.ramcon_type == "lasmicon":
- # LASMI
self.submodules.lasmicon = lasmicon.LASMIcon(phy_settings, sdram_geom, sdram_timing)
self.submodules.dficon1 = dfi.Interconnect(self.lasmicon.dfi, self.dfii.slave)
self.submodules.memtest_w = memtest.MemtestWriter(self.lasmixbar.get_master())
self.submodules.memtest_r = memtest.MemtestReader(self.lasmixbar.get_master())
- # Wishbone bridge: map SDRAM at 0x40000000 (shadow @0xc0000000)
+ # Wishbone bridge
self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(self.l2_size//4, self.lasmixbar.get_master())
- self.add_wb_slave(lambda a: a[26:29] == 4, self.wishbone2lasmi.wishbone)
- self.add_cpu_memory_region("sdram", 0x40000000,
+ self.add_wb_slave(mem_decoder(self.mem_map["sdram"]), self.wishbone2lasmi.wishbone)
+ self.add_cpu_memory_region("sdram", self.mem_map["sdram"],
2**self.lasmicon.lasmic.aw*self.lasmicon.lasmic.dw*self.lasmicon.lasmic.nbanks//8)
+ # MINICON
elif self.ramcon_type == "minicon":
self.submodules.minicon = sdramcon = Minicon(phy_settings, sdram_geom, sdram_timing)
self.submodules.dficon1 = dfi.Interconnect(sdramcon.dfi, self.dfii.slave)
sdram_width = flen(sdramcon.bus.dat_r)
if (sdram_width == 32):
- self.add_wb_slave(lambda a: a[26:29] == 4, sdramcon.bus)
+ self.add_wb_slave(mem_decoder(self.mem_map["sdram"]), sdramcon.bus)
elif (sdram_width < 32):
- self.submodules.dc = dc = wishbone.DownConverter(32, sdram_width)
+ self.submodules.dc = wishbone.DownConverter(32, sdram_width)
self.submodules.intercon = wishbone.InterconnectPointToPoint(dc.wishbone_o, sdramcon.bus)
- self.add_wb_slave(lambda a: a[26:29] == 4, dc.wishbone_i)
+ self.add_wb_slave(mem_decoder(self.mem_map["sdram"]), self.dc.wishbone_i)
else:
raise NotImplementedError("Unsupported SDRAM width of {} > 32".format(sdram_width))
- # map SDRAM at 0x40000000 (shadow @0xc0000000)
- self.add_cpu_memory_region("sdram", 0x40000000,
+ # Wishbone bridge
+ self.add_cpu_memory_region("sdram", self.mem_map["sdram"],
2**(sdram_geom.bank_a+sdram_geom.row_a+sdram_geom.col_a)*sdram_width//8)
else:
raise ValueError("Unsupported SDRAM controller type: {}".format(self.ramcon_type))
from misoclib import sdram, spiflash
from misoclib.sdram.phy import k7ddrphy
-from misoclib.gensoc import SDRAMSoC
+from misoclib.gensoc import SDRAMSoC, mem_decoder
from misoclib.liteeth.phy.gmii import LiteEthPHYGMII
from misoclib.liteeth.mac import LiteEthMAC
}
interrupt_map.update(BaseSoC.interrupt_map)
+ mem_map = {
+ "ethmac": 0x30000000, # (shadow @0xb0000000)
+ }
+ mem_map.update(BaseSoC.mem_map)
+
def __init__(self, platform, **kwargs):
BaseSoC.__init__(self, platform, **kwargs)
self.submodules.ethphy = LiteEthPHYGMII(platform.request("eth_clocks"), platform.request("eth"))
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
- self.add_wb_slave(lambda a: a[26:29] == 3, self.ethmac.bus)
- self.add_cpu_memory_region("ethmac_mem", 0xb0000000, 0x2000)
+ self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
+ self.add_cpu_memory_region("ethmac_mem", self.mem_map["ethmac"]+0x80000000, 0x2000)
default_subtarget = BaseSoC
from misoclib import sdram, mxcrg, norflash16, framebuffer, gpio
from misoclib.sdram.phy import s6ddrphy
-from misoclib.gensoc import SDRAMSoC
+from misoclib.gensoc import SDRAMSoC, mem_decoder
from misoclib.liteeth.phy.mii import LiteEthPHYMII
from misoclib.liteeth.mac import LiteEthMAC
}
interrupt_map.update(BaseSoC.interrupt_map)
+ mem_map = {
+ "ethmac": 0x30000000, # (shadow @0xb0000000)
+ }
+ mem_map.update(BaseSoC.mem_map)
+
def __init__(self, platform, **kwargs):
BaseSoC.__init__(self, platform, **kwargs)
self.submodules.ethphy = LiteEthPHYMII(platform.request("eth_clocks"), platform.request("eth"))
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
- self.add_wb_slave(lambda a: a[26:29] == 3, self.ethmac.bus)
- self.add_cpu_memory_region("ethmac_mem", 0xb0000000, 0x2000)
+ self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
+ self.add_cpu_memory_region("ethmac_mem", self.mem_map["ethmac"]+0x80000000, 0x2000)
def get_vga_dvi(platform):
try:
from migen.fhdl.std import *
from migen.bus import wishbone
-from misoclib.gensoc import GenSoC, IntegratedBIOS
+from misoclib.gensoc import GenSoC, IntegratedBIOS, mem_decoder
class _CRG(Module):
def __init__(self, clk_in):
]
class SimpleSoC(GenSoC, IntegratedBIOS):
+ mem_map = {
+ "sdram": 0x40000000, # (shadow @0xc0000000)
+ }
+ mem_map.update(GenSoC.mem_map)
+
def __init__(self, platform):
GenSoC.__init__(self, platform,
clk_freq=int((1/(platform.default_clk_period))*1000000000),
# use on-board SRAM as SDRAM
sys_ram_size = 16*1024
self.submodules.sys_ram = wishbone.SRAM(sys_ram_size)
- self.add_wb_slave(lambda a: a[27:29] == 2, self.sys_ram.bus)
- self.add_cpu_memory_region("sdram", 0x40000000, sys_ram_size)
+ self.add_wb_slave(mem_decoder(self.mem_map["sdram"]), self.sys_ram.bus)
+ self.add_cpu_memory_region("sdram", self.mem_map["sdram"], sys_ram_size)
default_subtarget = SimpleSoC
projects / litex.git / commitdiff