add explicit get of data inside sv_freg_t, float32_t etc.

diff --git a/riscv/insns/c_fsd.h b/riscv/insns/c_fsd.h
index cd8a3b0753ed23b0f08027ba8e3cd58a3fe92b2b..421caa836e9d25693ef589f12d288c6377ee75e8 100644 (file)
--- a/riscv/insns/c_fsd.h
+++ b/riscv/insns/c_fsd.h
@@ -1,4 +1,4 @@
 require_extension('C');
 require_extension('D');
 require_fp;
-MMU.store_uint64(insn.rvc_rs1s(), insn.rvc_ld_imm(), ((freg_t)RVC_FRS2S).v[0]); // RVC_RS1S
+MMU.store_uint64(insn.rvc_rs1s(), insn.rvc_ld_imm(), RVC_FRS2S.to_uint64()); // RVC_RS1S

diff --git a/riscv/insns/c_fsdsp.h b/riscv/insns/c_fsdsp.h
index ab3c69b83a396a823a08d128de91cf51e79f5368..e0b523e2ea1f5a264f00f4dab09c8c55e21ad8fc 100644 (file)
--- a/riscv/insns/c_fsdsp.h
+++ b/riscv/insns/c_fsdsp.h
@@ -1,4 +1,4 @@
 require_extension('C');
 require_extension('D');
 require_fp;
-MMU.store_uint64(rv_add(RVC_SP, insn.rvc_sdsp_imm()), ((freg_t)RVC_FRS2).v[0]);
+MMU.store_uint64(rv_add(RVC_SP, insn.rvc_sdsp_imm()), RVC_FRS2.to_uint64());

diff --git a/riscv/insns/c_fsw.h b/riscv/insns/c_fsw.h
index 988096b4a27b30782ca5aeb9a62005590da4224b..6cdd4191befe969c612e317f857b3013200f8d52 100644 (file)
--- a/riscv/insns/c_fsw.h
+++ b/riscv/insns/c_fsw.h
@@ -2,7 +2,7 @@ require_extension('C');
 if (xlen == 32) {
   require_extension('F');
   require_fp;
-  MMU.store_uint32(insn.rvc_rs1s(), insn.rvc_lw_imm(), ((freg_t)RVC_FRS2S).v[0]); //RVC_RS1S
+  MMU.store_uint32(insn.rvc_rs1s(), insn.rvc_lw_imm(), RVC_FRS2S.to_uint32()); //RVC_RS1S
 } else { // c.sd
   MMU.store_uint64(insn.rvc_rs1s(), insn.rvc_ld_imm(), RVC_RS2S); //RVC_RS1S, 
 }

diff --git a/riscv/insns/c_fswsp.h b/riscv/insns/c_fswsp.h
index fff75fccd45059f043cb5a131cec3d3dea396edd..2da961808f707744255578929e6aeed4d4a6f5a0 100644 (file)
--- a/riscv/insns/c_fswsp.h
+++ b/riscv/insns/c_fswsp.h
@@ -2,7 +2,7 @@ require_extension('C');
 if (xlen == 32) {
   require_extension('F');
   require_fp;
-  MMU.store_uint32(rv_add(RVC_SP, insn.rvc_swsp_imm()), ((freg_t)RVC_FRS2).v[0]);
+  MMU.store_uint32(rv_add(RVC_SP, insn.rvc_swsp_imm()), RVC_FRS2.to_uint32());
 } else { // c.sdsp
   MMU.store_uint64(rv_add(RVC_SP, insn.rvc_sdsp_imm()), RVC_RS2);
 }

diff --git a/riscv/insns/fmv_x_d.h b/riscv/insns/fmv_x_d.h
index e292ed04413068292f2e35b820bef804c495f871..1dd251160a2d3e9d3f91d20e82f877c8d4307808 100644 (file)
--- a/riscv/insns/fmv_x_d.h
+++ b/riscv/insns/fmv_x_d.h
@@ -1,4 +1,4 @@
 require_extension('D');
 require_rv64;
 require_fp;
-WRITE_RD(((freg_t)FRS1).v[0]);
+WRITE_RD(FRS1.to_uint64());

diff --git a/riscv/insns/fmv_x_w.h b/riscv/insns/fmv_x_w.h
index 987ce7b33dcd7bf29f7ed4f8a430efd9d004e5a3..616c7e9f3f5c05f89abab8c4bb7cd65a1aa21bc6 100644 (file)
--- a/riscv/insns/fmv_x_w.h
+++ b/riscv/insns/fmv_x_w.h
@@ -1,3 +1,3 @@
 require_extension('F');
 require_fp;
-WRITE_RD(sext32(sv_reg_t(((freg_t)FRS1).v[0])));
+WRITE_RD(sext32(sv_reg_t(FRS1.to_uint32())));

diff --git a/riscv/insns/fnmadd_s.h b/riscv/insns/fnmadd_s.h
index 476c9a44faba658663ba34e164d0a8d3dffb326a..c8fe05e6b1c5e55a321a96bc214e3d8ba99e4f2f 100644 (file)
--- a/riscv/insns/fnmadd_s.h
+++ b/riscv/insns/fnmadd_s.h
@@ -1,5 +1,5 @@
 require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_mulAdd(f32(((float32_t)f32(FRS1)).v ^ F32_SIGN), f32(FRS2), f32(((float32_t)f32(FRS3)).v ^ F32_SIGN)));
+WRITE_FRD(f32_mulAdd(f32(f32(FRS1).to_uint32() ^ F32_SIGN), f32(FRS2), f32(f32(FRS3).to_uint32() ^ F32_SIGN)));
 set_fp_exceptions;

diff --git a/riscv/insns/fsd.h b/riscv/insns/fsd.h
index 16b009b5fa6bd1d0a2da8a5084999c08898857fd..40b5b7313734c271b9c651bc784e047665171155 100644 (file)
--- a/riscv/insns/fsd.h
+++ b/riscv/insns/fsd.h
@@ -1,3 +1,3 @@
 require_extension('D');
 require_fp;
-MMU.store_uint64(insn.rs1(), insn.s_imm(), ((freg_t)FRS2).v[0]); // RS1
+MMU.store_uint64(insn.rs1(), insn.s_imm(), FRS2.to_uint64()); // RS1

diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index a5d994270050fb7fb38787e020ece20fe0cf8ba0..0327fb6ca686cafb075f6ec198dae25be6adad99 100644 (file)
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -895,3 +895,8 @@ uint32_t sv_freg_t::to_uint32() const&
     return reg.v[0];
 }
 
+uint32_t sv_float32_t::to_uint32() const&
+{
+    return reg.v;
+}
+

diff --git a/riscv/sv_reg.h b/riscv/sv_reg.h
index 0fc1fb02ac95efa262c08459a225c81c432c898a..da55fea20c655e8892f72e0956c100e13f53e5f1 100644 (file)
--- a/riscv/sv_reg.h
+++ b/riscv/sv_reg.h
@@ -108,6 +108,7 @@ public:
 public:
 
   operator float32_t() const& { return reg; }
+  uint32_t to_uint32() const&;
 };
 
 class sv_float64_t : public sv_regbase_t {