case AlphaISA::IPR_CC:
retval |= ipr[idx] & ULL(0xffffffff00000000);
- retval |= curTick & ULL(0x00000000ffffffff);
+ retval |= cpu->curCycle() & ULL(0x00000000ffffffff);
break;
case AlphaISA::IPR_VA:
#ifdef FULL_SYSTEM
BaseCPU::BaseCPU(Params *p)
- : SimObject(p->name), frequency(p->freq), checkInterrupts(true),
+ : SimObject(p->name), cycleTime(p->cycleTime), checkInterrupts(true),
params(p), number_of_threads(p->numberOfThreads), system(p->system)
#else
BaseCPU::BaseCPU(Params *p)
- : SimObject(p->name), params(p), number_of_threads(p->numberOfThreads)
+ : SimObject(p->name), cycleTime(p->cycleTime), params(p),
+ number_of_threads(p->numberOfThreads)
#endif
{
// add self to global list of CPUs
class BaseCPU : public SimObject
{
+ protected:
+ // CPU's clock period in terms of the number of ticks of curTime.
+ Tick cycleTime;
+
+ public:
+ inline Tick frequency() const { return Clock::Frequency / cycleTime; }
+ inline Tick cycles(int numCycles) const { return cycleTime * numCycles; }
+ inline Tick curCycle() const { return curTick / cycleTime; }
+
#ifdef FULL_SYSTEM
protected:
- Tick frequency;
uint64_t interrupts[NumInterruptLevels];
uint64_t intstatus;
bool check_interrupts() const { return intstatus != 0; }
uint64_t intr_status() const { return intstatus; }
-
- Tick getFreq() const { return frequency; }
#endif
protected:
Counter max_insts_all_threads;
Counter max_loads_any_thread;
Counter max_loads_all_threads;
- Tick freq;
+ Tick cycleTime;
bool functionTrace;
Tick functionTraceStart;
#ifdef FULL_SYSTEM
MemTest::tick()
{
if (!tickEvent.scheduled())
- tickEvent.schedule(curTick + 1);
+ tickEvent.schedule(curTick + cycles(1));
if (++noResponseCycles >= 500000) {
cerr << name() << ": deadlocked at cycle " << curTick << endl;
// register statistics
virtual void regStats();
+
+ inline Tick cycles(int numCycles) const { return numCycles; }
+
// main simulation loop (one cycle)
void tick();
status() == DcacheMissStall);
if (status() == Running && !tickEvent.scheduled())
- tickEvent.schedule(curTick + 1);
+ tickEvent.schedule(curTick + cycles(1));
}
SimObjectParam<Process *> workload;
#endif // FULL_SYSTEM
+ Param<int> cycle_time;
SimObjectParam<BaseMem *> icache;
SimObjectParam<BaseMem *> dcache;
INIT_PARAM(workload, "processes to run"),
#endif // FULL_SYSTEM
+ INIT_PARAM(cycle_time, "cpu cycle time"),
INIT_PARAM(icache, "L1 instruction cache object"),
INIT_PARAM(dcache, "L1 data cache object"),
INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
params->max_loads_any_thread = max_loads_any_thread;
params->max_loads_all_threads = max_loads_all_threads;
params->deferRegistration = defer_registration;
- params->freq = ticksPerSecond;
+ params->cycleTime = cycle_time;
params->functionTrace = function_trace;
params->functionTraceStart = function_trace_start;
params->icache_interface = (icache) ? icache->getInterface() : NULL;
TickEvent tickEvent;
/// Schedule tick event, regardless of its current state.
- void scheduleTickEvent(int delay)
+ void scheduleTickEvent(int numCycles)
{
if (tickEvent.squashed())
- tickEvent.reschedule(curTick + delay);
+ tickEvent.reschedule(curTick + cycles(numCycles));
else if (!tickEvent.scheduled())
- tickEvent.schedule(curTick + delay);
+ tickEvent.schedule(curTick + cycles(numCycles));
}
/// Unschedule tick event, regardless of its current state.
if (mainEventQueue.empty()) {
new SimExitEvent("Finshed Memory Trace");
} else {
- tickEvent.schedule(mainEventQueue.nextEventTime() + 1);
+ tickEvent.schedule(mainEventQueue.nextEventTime() + cycles(1));
}
} else {
- tickEvent.schedule(max(curTick + 1, nextCycle));
+ tickEvent.schedule(max(curTick + cycles(1), nextCycle));
}
}
MemInterface *dcache_interface,
MemTraceReader *data_trace);
+ inline Tick cycles(int numCycles) { return numCycles; }
+
/**
* Perform all the accesses for one cycle.
*/
using namespace std;
AlphaConsole::AlphaConsole(const string &name, SimConsole *cons, SimpleDisk *d,
- System *system, BaseCPU *cpu, Platform *p,
+ System *s, BaseCPU *c, Platform *p,
int num_cpus, MemoryController *mmu, Addr a,
HierParams *hier, Bus *bus)
- : PioDevice(name, p), disk(d), console(cons), addr(a)
+ : PioDevice(name, p), disk(d), console(cons), system(s), cpu(c), addr(a)
{
mmu->add_child(this, RangeSize(addr, size));
alphaAccess = new AlphaAccess;
alphaAccess->last_offset = size - 1;
- alphaAccess->kernStart = system->getKernelStart();
- alphaAccess->kernEnd = system->getKernelEnd();
- alphaAccess->entryPoint = system->getKernelEntry();
alphaAccess->version = ALPHA_ACCESS_VERSION;
alphaAccess->numCPUs = num_cpus;
- alphaAccess->mem_size = system->physmem->size();
- alphaAccess->cpuClock = cpu->getFreq() / 1000000;
- alphaAccess->intrClockFrequency = platform->intrFrequency();
alphaAccess->diskUnit = 1;
alphaAccess->diskCount = 0;
alphaAccess->align2 = 0;
}
+void
+AlphaConsole::init()
+{
+ alphaAccess->kernStart = system->getKernelStart();
+ alphaAccess->kernEnd = system->getKernelEnd();
+ alphaAccess->entryPoint = system->getKernelEntry();
+ alphaAccess->mem_size = system->physmem->size();
+ alphaAccess->cpuClock = cpu->frequency() / 1000000; // In MHz
+ alphaAccess->intrClockFrequency = platform->intrFrequency();
+}
+
Fault
AlphaConsole::read(MemReqPtr &req, uint8_t *data)
{
/** the system console (the terminal) is accessable from the console */
SimConsole *console;
+ /** a pointer to the system we are running in */
+ System *system;
+
+ /** a pointer to the CPU boot cpu */
+ BaseCPU *cpu;
+
Addr addr;
static const Addr size = 0x80; // equal to sizeof(alpha_access);
public:
/** Standard Constructor */
AlphaConsole(const std::string &name, SimConsole *cons, SimpleDisk *d,
- System *system, BaseCPU *cpu, Platform *platform,
+ System *s, BaseCPU *c, Platform *platform,
int num_cpus, MemoryController *mmu, Addr addr,
HierParams *hier, Bus *bus);
+ virtual void init();
+
/**
* memory mapped reads and writes
*/
using namespace std;
-EtherBus::EtherBus(const string &name, double rate, bool loop,
+EtherBus::EtherBus(const string &name, double speed, bool loop,
EtherDump *packet_dump)
- : SimObject(name), ticks_per_byte(rate), loopback(loop),
- event(&mainEventQueue, this),
- sender(0), dump(packet_dump)
-{ }
+ : SimObject(name), ticksPerByte(speed), loopback(loop),
+ event(&mainEventQueue, this), sender(0), dump(packet_dump)
+{
+}
void
EtherBus::txDone()
packet = pkt;
sender = sndr;
- int delay = (int)ceil(((double)pkt->length * ticks_per_byte) + 1.0);
+ int delay = (int)ceil(((double)pkt->length * ticksPerByte) + 1.0);
DPRINTF(Ethernet, "scheduling packet: delay=%d, (rate=%f)\n",
- delay, ticks_per_byte);
+ delay, ticksPerByte);
event.schedule(curTick + delay);
return true;
BEGIN_DECLARE_SIM_OBJECT_PARAMS(EtherBus)
Param<bool> loopback;
- Param<int> speed;
+ Param<double> speed;
SimObjectParam<EtherDump *> packet_dump;
END_DECLARE_SIM_OBJECT_PARAMS(EtherBus)
BEGIN_INIT_SIM_OBJECT_PARAMS(EtherBus)
- INIT_PARAM_DFLT(loopback,
- "send the packet back to the interface from which it came",
- true),
- INIT_PARAM_DFLT(speed, "bus speed in bits per second", 100000000),
- INIT_PARAM_DFLT(packet_dump, "object to dump network packets to", NULL)
+ INIT_PARAM(loopback, "send the packet back to the sending interface"),
+ INIT_PARAM(speed, "bus speed in ticks per byte"),
+ INIT_PARAM(packet_dump, "object to dump network packets to")
END_INIT_SIM_OBJECT_PARAMS(EtherBus)
CREATE_SIM_OBJECT(EtherBus)
{
- double rate = ((double)ticksPerSecond * 8.0) / (double)speed;
- return new EtherBus(getInstanceName(), rate, loopback, packet_dump);
+ return new EtherBus(getInstanceName(), speed, loopback, packet_dump);
}
REGISTER_SIM_OBJECT("EtherBus", EtherBus)
protected:
typedef std::list<EtherInt *> devlist_t;
devlist_t devlist;
- double ticks_per_byte;
+ double ticksPerByte;
bool loopback;
protected:
EtherDump *dump;
public:
- EtherBus(const std::string &name, double ticks_per_byte, bool loopback,
+ EtherBus(const std::string &name, double speed, bool loopback,
EtherDump *dump);
virtual ~EtherBus() {}
using namespace std;
EtherLink::EtherLink(const string &name, EtherInt *peer0, EtherInt *peer1,
- Tick speed, Tick dly, EtherDump *dump)
+ double rate, Tick delay, EtherDump *dump)
: SimObject(name)
{
- double rate = ((double)ticksPerSecond * 8.0) / (double)speed;
- Tick delay = dly * Clock::Int::us;
-
link[0] = new Link(name + ".link0", this, 0, rate, delay, dump);
link[1] = new Link(name + ".link1", this, 1, rate, delay, dump);
SimObjectParam<EtherInt *> int1;
SimObjectParam<EtherInt *> int2;
- Param<Tick> speed;
+ Param<double> speed;
Param<Tick> delay;
SimObjectParam<EtherDump *> dump;
INIT_PARAM(int1, "interface 1"),
INIT_PARAM(int2, "interface 2"),
- INIT_PARAM_DFLT(speed, "link speed in bits per second", 100000000),
- INIT_PARAM_DFLT(delay, "transmit delay of packets in us", 0),
- INIT_PARAM_DFLT(dump, "object to dump network packets to", NULL)
+ INIT_PARAM(speed, "link speed in bits per second"),
+ INIT_PARAM(delay, "transmit delay of packets in us"),
+ INIT_PARAM(dump, "object to dump network packets to")
END_INIT_SIM_OBJECT_PARAMS(EtherLink)
public:
EtherLink(const std::string &name, EtherInt *peer0, EtherInt *peer1,
- Tick speed, Tick delay, EtherDump *dump);
+ double rate, Tick delay, EtherDump *dump);
virtual ~EtherLink();
virtual void serialize(std::ostream &os);
DPRINTF(Ethernet, "bus busy...buffer for retransmission\n");
packetBuffer.push(packet);
if (!txEvent.scheduled())
- txEvent.schedule(curTick + 1000);
- } else if (dump)
+ txEvent.schedule(curTick + retryTime);
+ } else if (dump) {
dump->dump(packet);
+ }
}
}
}
if (!packetBuffer.empty() && !txEvent.scheduled())
- txEvent.schedule(curTick + 1000);
+ txEvent.schedule(curTick + retryTime);
}
//=====================================================================
using namespace std;
IdeDisk::IdeDisk(const string &name, DiskImage *img, PhysicalMemory *phys,
- int id, int delay)
- : SimObject(name), ctrl(NULL), image(img), physmem(phys),
+ int id, Tick delay)
+ : SimObject(name), ctrl(NULL), image(img), physmem(phys), diskDelay(delay),
dmaTransferEvent(this), dmaReadWaitEvent(this),
dmaWriteWaitEvent(this), dmaPrdReadEvent(this),
dmaReadEvent(this), dmaWriteEvent(this)
// Reset the device state
reset(id);
- // calculate disk delay in microseconds
- diskDelay = (delay * ticksPerSecond / 100000);
-
// fill out the drive ID structure
memset(&driveID, 0, sizeof(struct hd_driveid));
void
IdeDisk::doDmaRead()
{
+ /** @TODO we need to figure out what the delay actually will be */
Tick totalDiskDelay = diskDelay + (curPrd.getByteCount() / SectorSize);
+ DPRINTF(IdeDisk, "doDmaRead, diskDelay: %d totalDiskDelay: %d\n",
+ diskDelay, totalDiskDelay);
if (dmaInterface) {
if (dmaInterface->busy()) {
// reschedule after waiting period
void
IdeDisk::doDmaWrite()
{
+ /** @TODO we need to figure out what the delay actually will be */
Tick totalDiskDelay = diskDelay + (curPrd.getByteCount() / SectorSize);
+ DPRINTF(IdeDisk, "doDmaWrite, diskDelay: %d totalDiskDelay: %d\n",
+ diskDelay, totalDiskDelay);
+
if (dmaInterface) {
if (dmaInterface->busy()) {
// reschedule after waiting period
* @param disk_delay The disk delay in milliseconds
*/
IdeDisk(const std::string &name, DiskImage *img, PhysicalMemory *phys,
- int id, int disk_delay);
+ int id, Tick disk_delay);
/**
* Delete the data buffer.
: PciDev(p), ioEnable(false),
txFifo(p->tx_fifo_size), rxFifo(p->rx_fifo_size),
txPacket(0), rxPacket(0), txPacketBufPtr(NULL), rxPacketBufPtr(NULL),
- txXferLen(0), rxXferLen(0), txState(txIdle), txEnable(false),
- CTDD(false),
+ txXferLen(0), rxXferLen(0), cycleTime(p->cycle_time),
+ txState(txIdle), txEnable(false), CTDD(false),
txFragPtr(0), txDescCnt(0), txDmaState(dmaIdle), rxState(rxIdle),
rxEnable(false), CRDD(false), rxPktBytes(0),
rxFragPtr(0), rxDescCnt(0), rxDmaState(dmaIdle), extstsEnable(false),
}
- intrDelay = p->intr_delay * Clock::Int::us;
+ intrDelay = p->intr_delay;
dmaReadDelay = p->dma_read_delay;
dmaWriteDelay = p->dma_write_delay;
dmaReadFactor = p->dma_read_factor;
if (!txFifo.empty() && !txEvent.scheduled()) {
DPRINTF(Ethernet, "reschedule transmit\n");
- txEvent.schedule(curTick + 1000);
+ txEvent.schedule(curTick + retryTime);
}
}
DPRINTF(Ethernet, "transfer complete: data in txFifo...schedule xmit\n");
if (txEvent.scheduled())
- txEvent.reschedule(curTick + 1);
+ txEvent.reschedule(curTick + cycles(1));
else
- txEvent.schedule(curTick + 1);
+ txEvent.schedule(curTick + cycles(1));
}
bool
BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
Param<Addr> addr;
+ Param<Tick> cycle_time;
Param<Tick> tx_delay;
Param<Tick> rx_delay;
Param<Tick> intr_delay;
BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE)
INIT_PARAM(addr, "Device Address"),
- INIT_PARAM_DFLT(tx_delay, "Transmit Delay", 1000),
- INIT_PARAM_DFLT(rx_delay, "Receive Delay", 1000),
- INIT_PARAM_DFLT(intr_delay, "Interrupt Delay in microseconds", 0),
+ INIT_PARAM(cycle_time, "State machine processor frequency"),
+ INIT_PARAM(tx_delay, "Transmit Delay"),
+ INIT_PARAM(rx_delay, "Receive Delay"),
+ INIT_PARAM(intr_delay, "Interrupt Delay in microseconds"),
INIT_PARAM(mmu, "Memory Controller"),
INIT_PARAM(physmem, "Physical Memory"),
INIT_PARAM_DFLT(rx_filter, "Enable Receive Filter", true),
params->deviceNum = pci_dev;
params->functionNum = pci_func;
+ params->cycle_time = cycle_time;
params->intr_delay = intr_delay;
params->pmem = physmem;
params->tx_delay = tx_delay;
ns_desc txDescCache;
ns_desc rxDescCache;
+ /* state machine cycle time */
+ Tick cycleTime;
+ inline Tick cycles(int numCycles) const { return numCycles * cycleTime; }
+
/* tx State Machine */
TxState txState;
bool txEnable;
HierParams *hier;
Bus *header_bus;
Bus *payload_bus;
+ Tick cycle_time;
Tick intr_delay;
Tick tx_delay;
Tick rx_delay;
using namespace std;
+Platform::Platform(const string &name, IntrControl *intctrl, PciConfigAll *pci)
+ : SimObject(name), intrctrl(intctrl), pciconfig(pci)
+{
+}
+
+Platform::~Platform()
+{
+}
+
void
Platform::postPciInt(int line)
{
* Generic interface for platforms
*/
-#ifndef __PLATFORM_HH_
-#define __PLATFORM_HH_
+#ifndef __DEV_PLATFORM_HH__
+#define __DEV_PLATFORM_HH__
#include "sim/sim_object.hh"
#include "targetarch/isa_traits.hh"
public:
/** Pointer to the interrupt controller */
IntrControl *intrctrl;
+
/** Pointer to the PCI configuration space */
PciConfigAll *pciconfig;
/** Pointer to the UART, set by the uart */
Uart *uart;
- int interrupt_frequency;
-
public:
- Platform(const std::string &name, IntrControl *intctrl,
- PciConfigAll *pci, int intrFreq)
- : SimObject(name), intrctrl(intctrl), pciconfig(pci),
- interrupt_frequency(intrFreq) {}
- virtual ~Platform() {}
+ Platform(const std::string &name, IntrControl *intctrl, PciConfigAll *pci);
+ virtual ~Platform();
virtual void postConsoleInt() = 0;
virtual void clearConsoleInt() = 0;
virtual Tick intrFrequency() = 0;
virtual Addr pciToDma(Addr pciAddr) const;
};
-#endif // __PLATFORM_HH_
+#endif // __DEV_PLATFORM_HH__
// Sinic PCI Device
//
Base::Base(Params *p)
- : PciDev(p), rxEnable(false), txEnable(false),
- intrDelay(p->intr_delay * Clock::Int::us),
- intrTick(0), cpuIntrEnable(false), cpuPendingIntr(false), intrEvent(0),
- interface(NULL)
+ : PciDev(p), rxEnable(false), txEnable(false), cycleTime(p->cycle_time),
+ intrDelay(p->intr_delay), intrTick(0), cpuIntrEnable(false),
+ cpuPendingIntr(false), intrEvent(0), interface(NULL)
{
}
reschedule:
if (!txFifo.empty() && !txEvent.scheduled()) {
DPRINTF(Ethernet, "reschedule transmit\n");
- txEvent.schedule(curTick + 1000);
+ txEvent.schedule(curTick + retryTime);
}
}
DPRINTF(Ethernet, "transfer complete: data in txFifo...schedule xmit\n");
if (txEvent.scheduled())
- txEvent.reschedule(curTick + 1);
+ txEvent.reschedule(curTick + cycles(1));
else
- txEvent.schedule(curTick + 1);
+ txEvent.schedule(curTick + cycles(1));
}
bool
BEGIN_DECLARE_SIM_OBJECT_PARAMS(Device)
+ Param<Tick> cycle_time;
Param<Tick> tx_delay;
Param<Tick> rx_delay;
Param<Tick> intr_delay;
BEGIN_INIT_SIM_OBJECT_PARAMS(Device)
+ INIT_PARAM(cycle_time, "State machine cycle time"),
INIT_PARAM_DFLT(tx_delay, "Transmit Delay", 1000),
INIT_PARAM_DFLT(rx_delay, "Receive Delay", 1000),
INIT_PARAM_DFLT(intr_delay, "Interrupt Delay in microseconds", 0),
params->name = getInstanceName();
params->intr_delay = intr_delay;
params->physmem = physmem;
+ params->cycle_time = cycle_time;
params->tx_delay = tx_delay;
params->rx_delay = rx_delay;
params->mmu = mmu;
protected:
bool rxEnable;
bool txEnable;
+ Tick cycleTime;
+ inline Tick cycles(int numCycles) const { return numCycles * cycleTime; }
protected:
Tick intrDelay;
public:
struct Params : public PciDev::Params
{
+ Tick cycle_time;
Tick intr_delay;
};
using namespace std;
-Tsunami::Tsunami(const string &name, System *s,
- IntrControl *ic, PciConfigAll *pci, int intr_freq)
- : Platform(name, ic, pci, intr_freq), system(s)
+Tsunami::Tsunami(const string &name, System *s, IntrControl *ic,
+ PciConfigAll *pci)
+ : Platform(name, ic, pci), system(s)
{
// set the back pointer from the system to myself
system->platform = this;
SimObjectParam<System *> system;
SimObjectParam<IntrControl *> intrctrl;
SimObjectParam<PciConfigAll *> pciconfig;
- Param<int> interrupt_frequency;
END_DECLARE_SIM_OBJECT_PARAMS(Tsunami)
INIT_PARAM(system, "system"),
INIT_PARAM(intrctrl, "interrupt controller"),
- INIT_PARAM(pciconfig, "PCI configuration"),
- INIT_PARAM_DFLT(interrupt_frequency, "frequency of interrupts", 1024)
+ INIT_PARAM(pciconfig, "PCI configuration")
END_INIT_SIM_OBJECT_PARAMS(Tsunami)
CREATE_SIM_OBJECT(Tsunami)
{
- return new Tsunami(getInstanceName(), system, intrctrl, pciconfig,
- interrupt_frequency);
+ return new Tsunami(getInstanceName(), system, intrctrl, pciconfig);
}
REGISTER_SIM_OBJECT("Tsunami", Tsunami)
* @param intrFreq frequency that interrupts happen
*/
Tsunami(const std::string &name, System *s, IntrControl *intctrl,
- PciConfigAll *pci, int intrFreq);
+ PciConfigAll *pci);
/**
* Return the interrupting frequency to AlphaAccess
#define UNIX_YEAR_OFFSET 52
// Timer Event for Periodic interrupt of RTC
-TsunamiIO::RTCEvent::RTCEvent(Tsunami* t)
- : Event(&mainEventQueue), tsunami(t)
+TsunamiIO::RTCEvent::RTCEvent(Tsunami* t, Tick i)
+ : Event(&mainEventQueue), tsunami(t), interval(i)
{
DPRINTF(MC146818, "RTC Event Initilizing\n");
- schedule(curTick + ticksPerSecond/RTC_RATE);
+ schedule(curTick + interval);
}
void
TsunamiIO::RTCEvent::process()
{
DPRINTF(MC146818, "RTC Timer Interrupt\n");
- schedule(curTick + ticksPerSecond/RTC_RATE);
+ schedule(curTick + interval);
//Actually interrupt the processor here
tsunami->cchip->postRTC();
}
const char *
TsunamiIO::RTCEvent::description()
{
- return "tsunami RTC 1024Hz interrupt";
+ return "tsunami RTC interrupt";
}
void
void
TsunamiIO::ClockEvent::Program(int count)
{
- DPRINTF(Tsunami, "Timer set to curTick + %d\n", count);
+ DPRINTF(Tsunami, "Timer set to curTick + %d\n", count * interval);
schedule(curTick + count * interval);
status = 0;
}
TsunamiIO::TsunamiIO(const string &name, Tsunami *t, time_t init_time,
Addr a, MemoryController *mmu, HierParams *hier, Bus *bus,
- Tick pio_latency)
- : PioDevice(name, t), addr(a), tsunami(t), rtc(t)
+ Tick pio_latency, Tick ci)
+ : PioDevice(name, t), addr(a), clockInterval(ci), tsunami(t), rtc(t, ci)
{
mmu->add_child(this, RangeSize(addr, size));
picInterrupting = false;
}
+Tick
+TsunamiIO::frequency() const
+{
+ return Clock::Frequency / clockInterval;
+}
+
void
TsunamiIO::set_time(time_t t)
{
SimObjectParam<Bus*> io_bus;
Param<Tick> pio_latency;
SimObjectParam<HierParams *> hier;
+ Param<Tick> frequency;
END_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO)
BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
INIT_PARAM(tsunami, "Tsunami"),
- INIT_PARAM_DFLT(time, "System time to use "
- "(0 for actual time, default is 1/1/06", ULL(1136073600)),
+ INIT_PARAM(time, "System time to use (0 for actual time"),
INIT_PARAM(mmu, "Memory Controller"),
INIT_PARAM(addr, "Device Address"),
INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
- INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
+ INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams),
+ INIT_PARAM(frequency, "clock interrupt frequency")
END_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
CREATE_SIM_OBJECT(TsunamiIO)
{
return new TsunamiIO(getInstanceName(), tsunami, time, addr, mmu, hier,
- io_bus, pio_latency);
+ io_bus, pio_latency, frequency);
}
REGISTER_SIM_OBJECT("TsunamiIO", TsunamiIO)
#include "dev/tsunami.hh"
#include "sim/eventq.hh"
-/** How often the RTC interrupts */
-static const int RTC_RATE = 1024;
-
/*
* Tsunami I/O device is a catch all for all the south bridge stuff we care
* to implement.
protected:
/** A pointer back to tsunami to create interrupt the processor. */
Tsunami* tsunami;
+ Tick interval;
+
public:
- /** RTC Event initializes the RTC event by scheduling an event
- * RTC_RATE times pre second. */
- RTCEvent(Tsunami* t);
+ /**
+ * RTC Event initializes the RTC event by scheduling an event
+ * RTC_RATE times pre second.
+ */
+ RTCEvent(Tsunami* t, Tick i);
/**
* Interrupth the processor and reschedule the event.
/** Is the pic interrupting right now or not. */
bool picInterrupting;
+ Tick clockInterval;
+
/** A pointer to the Tsunami device which be belong to */
Tsunami *tsunami;
* Return the freqency of the RTC
* @return interrupt rate of the RTC
*/
- Tick frequency() const { return RTC_RATE; }
+ Tick frequency() const;
/**
* Initialize all the data for devices supported by Tsunami I/O.
*/
TsunamiIO(const std::string &name, Tsunami *t, time_t init_time,
Addr a, MemoryController *mmu, HierParams *hier, Bus *bus,
- Tick pio_latency);
+ Tick pio_latency, Tick ci);
/**
* Create the tm struct from seconds since 1970
physmem->dma_addr(paddr, sizeof(uint64_t));
if (est_cycle_frequency)
- *(uint64_t *)est_cycle_frequency = htoa(ticksPerSecond);
+ *(uint64_t *)est_cycle_frequency =
+ Clock::Frequency / p->boot_cpu_frequency;
}
uint8_t *loops_per_jiffy =
physmem->dma_addr(paddr, sizeof(uint32_t));
- Tick cpuFreq = xc->cpu->getFreq();
- Tick intrFreq = platform->interrupt_frequency;
+ Tick cpuFreq = xc->cpu->frequency();
+ Tick intrFreq = platform->intrFrequency();
*(uint32_t *)loops_per_jiffy =
(uint32_t)((cpuFreq / intrFreq) * 0.9988);
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(LinuxSystem)
+ Param<Tick> boot_cpu_frequency;
SimObjectParam<MemoryController *> memctrl;
SimObjectParam<PhysicalMemory *> physmem;
BEGIN_INIT_SIM_OBJECT_PARAMS(LinuxSystem)
+ INIT_PARAM(boot_cpu_frequency, "Frequency of the boot CPU"),
INIT_PARAM(memctrl, "memory controller"),
INIT_PARAM(physmem, "phsyical memory"),
INIT_PARAM(kernel, "file that contains the kernel code"),
{
System::Params *p = new System::Params;
p->name = getInstanceName();
+ p->boot_cpu_frequency = boot_cpu_frequency;
p->memctrl = memctrl;
p->physmem = physmem;
p->kernel_path = kernel;
#include "base/loader/symtab.hh"
#include "base/trace.hh"
+#include "cpu/base_cpu.hh"
#include "cpu/exec_context.hh"
#include "kern/tru64/tru64_events.hh"
#include "kern/tru64/tru64_system.hh"
BEGIN_DECLARE_SIM_OBJECT_PARAMS(Tru64System)
+ Param<Tick> boot_cpu_frequency;
SimObjectParam<MemoryController *> memctrl;
SimObjectParam<PhysicalMemory *> physmem;
BEGIN_INIT_SIM_OBJECT_PARAMS(Tru64System)
+ INIT_PARAM(boot_cpu_frequency, "frequency of the boot cpu"),
INIT_PARAM(memctrl, "memory controller"),
INIT_PARAM(physmem, "phsyical memory"),
INIT_PARAM(kernel, "file that contains the kernel code"),
{
System::Params *p = new System::Params;
p->name = getInstanceName();
+ p->boot_cpu_frequency = boot_cpu_frequency;
p->memctrl = memctrl;
p->physmem = physmem;
p->kernel_path = kernel;
except:
return False
-
class_decorator = 'M5M5_SIMOBJECT_'
expr_decorator = 'M5M5_EXPRESSION_'
dot_decorator = '_M5M5_DOT_'
'parent.any matched more than one: %s %s' % \
(obj.path, child.path)
obj = child
+ for param in self.params:
+ if isConfigNode(param.ptype):
+ continue
+ if issubclass(param.ptype, realtype):
+ if obj is not None:
+ raise AttributeError, \
+ 'parent.any matched more than one: %s' % obj.path
+ obj = param.value
return obj, obj is not None
try:
return Proxy.getindex(value, index), True
elif obj.param_names.has_key(last):
value = obj.param_names[last]
- realtype._convert(value.value)
+ #realtype._convert(value.value)
return Proxy.getindex(value.value, index), True
except KeyError:
pass
raise AttributeError, 'Parameter with no value'
value = param.convert(param.value)
+ if hasattr(value, 'relative') and value.relative and value:
+ if param.name == 'cycle_time':
+ start = self.parent
+ else:
+ start = self
+ val = start.unproxy(parent.cycle_time,
+ (Frequency, Latency, ClockPeriod))
+ value.clock = Frequency._convert(val)
string = param.string(value)
except Exception, e:
- msg = 'exception in %s:%s\n%s' % (self.path, param.name, e)
+ msg = 'exception in %s:%s=%s\n%s' % (self.path, param.name,
+ value, e)
e.args = (msg, )
raise
raise AttributeError, 'Parameter with no value'
value = param.convert(param.value)
+ if param.ptype in (Frequency, Latency, ClockPeriod):
+ val = self.parent.unproxy(parent.frequency, Frequency)
+ param.clock = Frequency._convert(val)
string = param.string(value)
except Exception, e:
msg = 'exception in %s:%s\n%s' % (self.name, param.name, e)
_convert = classmethod(_convert)
def _string(cls, value):
- return '%d' % int(value)
+ return '%d' % int(round(value))
_string = classmethod(_string)
class ClockPeriod(float,ParamType):
_cpp_param_decl = 'Tick'
def __new__(cls, value):
+ absolute = False
relative = False
try:
val = toClockPeriod(value)
except ValueError, e:
- relative = True
if value.endswith('f'):
val = float(value[:-1])
if val:
val = 1 / val
+ relative = True
elif value.endswith('c'):
val = float(value[:-1])
+ relative = True
+ elif value.endswith('t'):
+ val = float(value[:-1])
+ absolute = True
else:
raise e
self = super(cls, ClockPeriod).__new__(cls, val)
+ self.absolute = absolute
self.relative = relative
return self
_convert = classmethod(_convert)
def _string(cls, value):
- if not value.relative:
- value *= root_frequency
+ if value and not value.absolute:
+ if value.relative:
+ base = root_frequency / value.clock
+ else:
+ base = root_frequency
+ value *= base
- return '%d' % int(value)
+ return '%d' % int(round(value))
_string = classmethod(_string)
class Frequency(float,ParamType):
_convert = classmethod(_convert)
def _string(cls, value):
- if not value.relative:
- value = root_frequency / value
+ if value:
+ if value.relative:
+ base = root_frequency / value.clock
+ else:
+ base = root_frequency
+
+ value = base / value
- return '%d' % int(value)
+ return '%d' % int(round(value))
_string = classmethod(_string)
class Latency(float,ParamType):
_cpp_param_decl = 'Tick'
def __new__(cls, value):
+ absolute = False
relative = False
try:
val = toLatency(value)
if value.endswith('c'):
val = float(value[:-1])
relative = True
+ elif value.endswith('t'):
+ val = float(value[:-1])
+ absolute = True
else:
raise e
self = super(cls, Latency).__new__(cls, val)
+ self.absolute = absolute
self.relative = relative
return self
_convert = classmethod(_convert)
def _string(cls, value):
- if not value.relative:
- value *= root_frequency
- return '%d' % value
+ if value and not value.absolute:
+ if value.relative:
+ base = root_frequency / value.clock
+ else:
+ base = root_frequency
+ value *= base
+ return '%d' % int(round(value))
_string = classmethod(_string)
+class NetworkBandwidth(float,ParamType):
+ _cpp_param_decl = 'float'
+ def __new__(cls, value):
+ val = toNetworkBandwidth(value) / 8.0
+ return super(cls, NetworkBandwidth).__new__(cls, val)
+
+ def _convert(cls, value):
+ return cls(value)
+ _convert = classmethod(_convert)
+
+ def _string(cls, value):
+ value = root_frequency / value
+ return '%f' % value
+ _string = classmethod(_string)
+
+class MemoryBandwidth(float,ParamType):
+ _cpp_param_decl = 'float'
+ def __new__(self, value):
+ val = toMemoryBandwidth(value)
+ return super(cls, MemoryBandwidth).__new__(cls, val)
+
+ def _convert(cls, value):
+ return cls(value)
+ _convert = classmethod(_convert)
+
+ def _string(cls, value):
+ value = root_frequency / value
+ return '%f' % value
+ _string = classmethod(_string)
# Some memory range specifications use this as a default upper bound.
MaxAddr = Addr.max
'Int32', 'UInt32', 'Int64', 'UInt64',
'Counter', 'Addr', 'Tick', 'Percent',
'MemorySize', 'RootFrequency', 'Frequency', 'Latency',
- 'ClockPeriod',
+ 'ClockPeriod', 'NetworkBandwidth', 'MemoryBandwidth',
'Range', 'AddrRange', 'MaxAddr', 'MaxTick', 'AllMemory', 'NULL',
'NextEthernetAddr', 'instantiate']
defer_registration = Param.Bool(False,
"defer registration with system (for sampling)")
+
+ cycle_time = Param.ClockPeriod(parent.frequency, "clock speed")
block_size = Param.Int("block size in bytes")
compressed_bus = Param.Bool(False,
"This cache connects to a compressed memory")
- compression_latency = Param.Int(0,
+ compression_latency = Param.Latency('0c',
"Latency in cycles of compression algorithm")
do_copy = Param.Bool(False, "perform fast copies in the cache")
hash_delay = Param.Int(1, "time in cycles of hash access")
simobj BaseSystem(SimObject):
type = 'BaseSystem'
abstract = True
+ boot_cpu_frequency = Param.ClockPeriod(parent.cpu[0].cycle_time,
+ "Boot Processor Frequency")
memctrl = Param.MemoryController(parent.any, "memory controller")
physmem = Param.PhysicalMemory(parent.any, "phsyical memory")
kernel = Param.String("file that contains the kernel code")
type = 'EtherLink'
int1 = Param.EtherInt("interface 1")
int2 = Param.EtherInt("interface 2")
- delay = Param.Tick(0, "transmit delay of packets in us")
- speed = Param.Tick(100000000, "link speed in bits per second")
+ delay = Param.Latency('0us', "packet transmit delay")
+ speed = Param.NetworkBandwidth('100Mbps', "link speed")
dump = Param.EtherDump(NULL, "dump object")
simobj EtherBus(SimObject):
type = 'EtherBus'
- loopback = Param.Bool(True,
- "send packet back to the interface from which it came")
+ loopback = Param.Bool(True, "send packet back to the sending interface")
dump = Param.EtherDump(NULL, "dump object")
- speed = Param.UInt64(100000000, "bus speed in bits per second")
+ speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second")
simobj EtherTap(EtherInt):
type = 'EtherTap'
dma_data_free = Param.Bool(False, "DMA of Data is free")
dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
- dma_read_delay = Param.Tick(0, "fixed delay for dma reads")
- dma_read_factor = Param.Tick(0, "multiplier for dma reads")
- dma_write_delay = Param.Tick(0, "fixed delay for dma writes")
- dma_write_factor = Param.Tick(0, "multiplier for dma writes")
+ dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
+ dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
+ dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
+ dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
rx_filter = Param.Bool(True, "Enable Receive Filter")
- rx_delay = Param.Tick(1000, "Receive Delay")
- tx_delay = Param.Tick(1000, "Transmit Delay")
+ rx_delay = Param.Latency('1us', "Receive Delay")
+ tx_delay = Param.Latency('1us', "Transmit Delay")
- intr_delay = Param.Tick(0, "Interrupt Delay in microseconds")
+ intr_delay = Param.Latency('0us', "Interrupt Delay")
payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
physmem = Param.PhysicalMemory(parent.any, "Physical Memory")
tlaser = Param.Turbolaser(parent.any, "Turbolaser")
hardware_address = Param.EthernetAddr(NextEthernetAddr,
"Ethernet Hardware Address")
+ cycle_time = Param.Frequency('100MHz', "State machine processor frequency")
+
dma_data_free = Param.Bool(False, "DMA of Data is free")
dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
- dma_read_delay = Param.Tick(0, "fixed delay for dma reads")
- dma_read_factor = Param.Tick(0, "multiplier for dma reads")
- dma_write_delay = Param.Tick(0, "fixed delay for dma writes")
- dma_write_factor = Param.Tick(0, "multiplier for dma writes")
+ dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
+ dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
+ dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
+ dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
rx_filter = Param.Bool(True, "Enable Receive Filter")
- rx_delay = Param.Tick(1000, "Receive Delay")
- tx_delay = Param.Tick(1000, "Transmit Delay")
+ rx_delay = Param.Latency('1us', "Receive Delay")
+ tx_delay = Param.Latency('1us', "Transmit Delay")
rx_fifo_size = Param.MemorySize('128kB', "max size in bytes of rxFifo")
tx_fifo_size = Param.MemorySize('128kB', "max size in bytes of txFifo")
- intr_delay = Param.Tick(0, "Interrupt Delay in microseconds")
+ intr_delay = Param.Latency('0us', "Interrupt Delay in microseconds")
payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
physmem = Param.PhysicalMemory(parent.any, "Physical Memory")
simobj IdeDisk(SimObject):
type = 'IdeDisk'
- delay = Param.Tick(1, "Fixed disk delay in microseconds")
+ delay = Param.Latency('1us', "Fixed disk delay in microseconds")
driveID = Param.IdeID('master', "Drive ID")
image = Param.DiskImage("Disk image")
physmem = Param.PhysicalMemory(parent.any, "Physical memory")
simobj Platform(SimObject):
type = 'Platform'
abstract = True
- interrupt_frequency = Param.Tick(1200, "frequency of interrupts")
intrctrl = Param.IntrControl(parent.any, "interrupt controller")
type = 'Tsunami'
pciconfig = Param.PciConfigAll("PCI configuration")
system = Param.BaseSystem(parent.any, "system")
- interrupt_frequency = Param.Int(1024, "frequency of interrupts")
simobj TsunamiCChip(FooPioDevice):
type = 'TsunamiCChip'
time = Param.UInt64(1136073600,
"System time to use (0 for actual time, default is 1/1/06)")
tsunami = Param.Tsunami(parent.any, "Tsunami")
+ frequency = Param.Frequency('1024Hz', "frequency of interrupts")
simobj TsunamiPChip(FooPioDevice):
type = 'TsunamiPChip'
if (nextTick() > when)
break;
- assert(head->when() >= when && "event scheduled in the past");
+ /**
+ * @todo this assert is a good bug catcher. I need to
+ * make it true again.
+ */
+ //assert(head->when() >= when && "event scheduled in the past");
serviceOne();
}
}
// first exec context for this process... initialize & enable
ExecContext *xc = execContexts[0];
- // mark this context as active.
- // activate with zero delay so that we start ticking right
- // away on cycle 0
+ // mark this context as active so it will start ticking.
xc->activate(0);
}
#include "kern/system_events.hh"
#include "sim/sim_object.hh"
+class BaseCPU;
+class ExecContext;
+class GDBListener;
class MemoryController;
+class ObjectFile;
class PhysicalMemory;
class Platform;
class RemoteGDB;
-class GDBListener;
class SymbolTable;
-class ObjectFile;
-class ExecContext;
namespace Kernel { class Binning; }
class System : public SimObject
struct Params
{
std::string name;
+ Tick boot_cpu_frequency;
MemoryController *memctrl;
PhysicalMemory *physmem;
uint64_t init_param;
outputStream = simout.find(output_file);
Root *root = new Root(getInstanceName());
- ticksPerSecond = frequency;
-
using namespace Clock;
Frequency = frequency;
Float::s = static_cast<double>(Frequency);
projects / gem5.git / commitdiff