add future potential section on DD-FF-Rc=1

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index cb26ac0cf6dbe472c5b9b0afcfbcf20317823b02..d2747b2db4f14dbd27199c7d9e13a8dd5ecce3b2 100644 (file)
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -513,6 +513,15 @@ the pairs, and consequently allowing Vectorised Data-Dependent Fail-First is
 useful.  Care should be taken however when VL is truncated in Vertical-First
 Mode.
 
+**Future potential**
+
+Although Rc=1 on LD/ST is a rare occurrence at present, future versions
+of Power ISA *might* conceivably have Rc=1 LD/ST Scalar instructions, and
+with the SVP64 Vectorisation Prefixing being itself a RISC-paradigm that
+is itself fully-independent of the Scalar Suffix Defined Words, prohibiting
+Rc=1 Data-Dependent Mode on future potential LD/ST operations is not
+strategically sound.
+
 ## LOAD/STORE Elwidths <a name="elwidth"></a>
 
 Loads and Stores are almost unique in that the Power Scalar ISA