Use singular for disabling of DRAM or BRAM inference.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

diff --git a/manual/command-reference-manual.tex b/manual/command-reference-manual.tex
index bb9d7238c1ec3fe5f5b6f63f5f2230a6e91e39b3..bed6326e2446a94fabaa79f967e709dce66aa3d9 100644 (file)
--- a/manual/command-reference-manual.tex
+++ b/manual/command-reference-manual.tex
@@ -4244,15 +4244,9 @@ compatible with 7-Series Xilinx devices.
         is omitted if this parameter is not specified.
 
     -vpr
-        generate an output netlist (and BLIF file) suitable for VPR.
+        generate an output netlist (and BLIF file) suitable for VPR
         (this feature is experimental and incomplete)
 
-    -nobrams
-        disable infering of block rams
-
-    -nodrams
-        disable infering of distributed rams
-
     -run <from_label>:<to_label>
         only run the commands between the labels (see below). an empty
         from label is synonymous to 'begin', and empty to label is
@@ -4280,11 +4274,11 @@ The following commands are executed by this synthesis command:
     coarse:
         synth -run coarse
 
-    bram: (only executed when '-nobrams' is not given)
+    bram:
         memory_bram -rules +/xilinx/brams.txt
         techmap -map +/xilinx/brams_map.v
 
-    dram: (only executed when '-nodrams' is not given)
+    dram:
         memory_bram -rules +/xilinx/drams.txt
         techmap -map +/xilinx/drams_map.v
 
@@ -4294,17 +4288,16 @@ The following commands are executed by this synthesis command:
         dffsr2dff
         dff2dffe
         opt -full
-        techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v
+        techmap -map +/techmap.v -map +/xilinx/arith_map.v
         opt -fast
 
     map_luts:
-        abc -luts 2:2,3,6:5,10,20 [-dff] (without '-vpr' only!)
-        abc -lut 5 [-dff] (with '-vpr' only!)
+        abc -luts 2:2,3,6:5,10,20 [-dff]
         clean
 
     map_cells:
         techmap -map +/xilinx/cells_map.v (with -D NO_LUT in vpr mode)
-        dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT
+        dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT
         clean
 
     check:

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 12ad9fdaf5b31a3a871865636d0ee516e42accd3..9e7559944856791afe0f1d9d3666e77a4d1cf0d3 100644 (file)
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -63,10 +63,10 @@ struct SynthXilinxPass : public Pass
                log("        generate an output netlist (and BLIF file) suitable for VPR\n");
                log("        (this feature is experimental and incomplete)\n");
                log("\n");
-               log("    -nobrams\n");
+               log("    -nobram\n");
                log("        disable infering of block rams\n");
                log("\n");
-               log("    -nodrams\n");
+               log("    -nodram\n");
                log("        disable infering of distributed rams\n");
                log("\n");
                log("    -run <from_label>:<to_label>\n");
@@ -96,11 +96,11 @@ struct SynthXilinxPass : public Pass
                log("    coarse:\n");
                log("        synth -run coarse\n");
                log("\n");
-               log("    bram: (only executed when '-nobrams' is not given)\n");
+               log("    bram: (only executed when '-nobram' is not given)\n");
                log("        memory_bram -rules +/xilinx/brams.txt\n");
                log("        techmap -map +/xilinx/brams_map.v\n");
                log("\n");
-               log("    dram: (only executed when '-nodrams' is not given)\n");
+               log("    dram: (only executed when '-nodram' is not given)\n");
                log("        memory_bram -rules +/xilinx/drams.txt\n");
                log("        techmap -map +/xilinx/drams_map.v\n");
                log("\n");
@@ -144,8 +144,8 @@ struct SynthXilinxPass : public Pass
                bool flatten = false;
                bool retime = false;
                bool vpr = false;
-               bool noBrams = false;
-               bool noDrams = false;
+               bool nobram = false;
+               bool nodram = false;
 
                size_t argidx;
                for (argidx = 1; argidx < args.size(); argidx++)
@@ -182,12 +182,12 @@ struct SynthXilinxPass : public Pass
                                vpr = true;
                                continue;
                        }
-                       if (args[argidx] == "-nobrams") {
-                               noBrams = true;
+                       if (args[argidx] == "-nobram") {
+                               nobram = true;
                                continue;
                        }
-                       if (args[argidx] == "-nodrams") {
-                               noDrams = true;
+                       if (args[argidx] == "-nodram") {
+                               nodram = true;
                                continue;
                        }
                        break;
@@ -212,7 +212,7 @@ struct SynthXilinxPass : public Pass
 
                        Pass::call(design, "read_verilog -lib +/xilinx/cells_xtra.v");
 
-                       if (!noBrams) {
+                       if (!nobram) {
                                Pass::call(design, "read_verilog -lib +/xilinx/brams_bb.v");
                        }
 
@@ -232,7 +232,7 @@ struct SynthXilinxPass : public Pass
 
                if (check_label(active, run_from, run_to, "bram"))
                {
-                       if (!noBrams) {
+                       if (!nobram) {
                                Pass::call(design, "memory_bram -rules +/xilinx/brams.txt");
                                Pass::call(design, "techmap -map +/xilinx/brams_map.v");
                        }
@@ -240,7 +240,7 @@ struct SynthXilinxPass : public Pass
 
                if (check_label(active, run_from, run_to, "dram"))
                {
-                       if (!noDrams) {
+                       if (!nodram) {
                                Pass::call(design, "memory_bram -rules +/xilinx/drams.txt");
                                Pass::call(design, "techmap -map +/xilinx/drams_map.v");
                        }