[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing
+cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing
egid=100
env=
errout=cerr
All Rights Reserved
-M5 compiled Feb 8 2011 00:58:32
-M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip
-M5 started Feb 8 2011 00:58:34
+M5 compiled Feb 12 2011 02:22:23
+M5 revision 5e76f9de6972 7961 default qtip tip x86branchdetectstats.patch
+M5 started Feb 12 2011 02:22:27
M5 executing on burrito
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/o3-timing
+command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 758990697000 because target called exit()
+Exiting @ tick 766217705000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 240879 # Simulator instruction rate (inst/s)
-host_mem_usage 232888 # Number of bytes of host memory used
-host_seconds 6731.58 # Real time elapsed on the host
-host_tick_rate 112750685 # Simulator tick rate (ticks/s)
+host_inst_rate 123498 # Simulator instruction rate (inst/s)
+host_mem_usage 236748 # Number of bytes of host memory used
+host_seconds 13129.74 # Real time elapsed on the host
+host_tick_rate 58357436 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1621493982 # Number of instructions simulated
-sim_seconds 0.758991 # Number of seconds simulated
-sim_ticks 758990697000 # Number of ticks simulated
+sim_seconds 0.766218 # Number of seconds simulated
+sim_ticks 766217705000 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 123829137 # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 124444739 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 169776992 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 171183773 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect 5933451 # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 124445048 # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 124445048 # Number of BP lookups
+system.cpu.BPredUnit.condIncorrect 8003535 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 180455810 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 180455810 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 107161579 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 4428744 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 7534042 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 1488500908 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean 1.089347 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev 1.266465 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 1432274296 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 1.132111 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 1.344268 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 544771983 36.60% 36.60% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1 603082048 40.52% 77.11% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2 142955782 9.60% 86.72% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3 121627881 8.17% 94.89% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4 42142525 2.83% 97.72% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5 19097450 1.28% 99.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6 4632040 0.31% 99.32% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7 5762455 0.39% 99.70% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 4428744 0.30% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 536173455 37.44% 37.44% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 547306108 38.21% 75.65% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 130197340 9.09% 84.74% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 136647601 9.54% 94.28% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 42821104 2.99% 97.27% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 22915800 1.60% 98.87% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 3037283 0.21% 99.08% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 5641563 0.39% 99.47% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 7534042 0.53% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 1488500908 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 1432274296 # Number of insts commited each cycle
system.cpu.commit.COM:count 1621493982 # Number of instructions committed
system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 607228182 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 5933482 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 8003567 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 1621493982 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 174503493 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 729601482 # The number of squashed insts skipped by commit
system.cpu.committedInsts 1621493982 # Number of Instructions Simulated
system.cpu.committedInsts_total 1621493982 # Number of Instructions Simulated
-system.cpu.cpi 0.936162 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.936162 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 328666076 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 10263.411891 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7269.320090 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 328458033 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 2135231000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.000633 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 208043 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 1354 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 1502488500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.000629 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 206689 # number of ReadReq MSHR misses
+system.cpu.cpi 0.945076 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.945076 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 330979138 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 10103.492713 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7153.561618 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 330761084 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 2203107000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.000659 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 218054 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 3264 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 1536513500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.000649 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 214790 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 19664.658707 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 9970.057484 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 186942755 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 24449109500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.006607 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 1243302 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 995928 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 2466333000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.001315 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 247374 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 19459.417847 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10004.386505 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 186948986 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 24072681495 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.006574 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 1237071 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 986986 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 2501946999 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.001329 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 250085 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 15814.402211 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 1135.086514 # Average number of references to valid blocks.
+system.cpu.dcache.avg_blocked_cycles::no_targets 16007.596007 # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 1113.654359 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 29308 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 29555 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 463488500 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 473104500 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 516852133 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 18317.037300 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 8740.684663 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 515400788 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 26584340500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.002808 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 1451345 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 997282 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 3968821500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.000879 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 454063 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 519165195 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 18057.409841 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 8687.196556 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 517710070 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 26275788495 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.002803 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 1455125 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 990250 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 4038460499 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.000895 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 464875 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.999777 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4095.087002 # Average occupied blocks per context
-system.cpu.dcache.overall_accesses 516852133 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 18317.037300 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 8740.684663 # average overall mshr miss latency
+system.cpu.dcache.occ_%::0 0.999796 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4095.162912 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses 519165195 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 18057.409841 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 8687.196556 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 515400788 # number of overall hits
-system.cpu.dcache.overall_miss_latency 26584340500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.002808 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 1451345 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 997282 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 3968821500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.000879 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 454063 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 517710070 # number of overall hits
+system.cpu.dcache.overall_miss_latency 26275788495 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.002803 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 1455125 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 990250 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 4038460499 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.000895 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 464875 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 449967 # number of replacements
-system.cpu.dcache.sampled_refs 454063 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 460779 # number of replacements
+system.cpu.dcache.sampled_refs 464875 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4095.087002 # Cycle average of tags in use
-system.cpu.dcache.total_refs 515400788 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 331273000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 403776 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 134525635 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts 1844468999 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 346793246 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 965499551 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 29266045 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles 41682476 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 124445048 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 129713560 # Number of cache lines fetched
-system.cpu.fetch.Cycles 1050276779 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 844154 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 1022007635 # Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles 46 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles 12829021 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.081981 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 129713560 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 123829137 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 0.673268 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 1517766953 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.229744 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 1.282154 # Number of instructions fetched each cycle (Total)
+system.cpu.dcache.tagsinuse 4095.162912 # Cycle average of tags in use
+system.cpu.dcache.total_refs 517710070 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 317835000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 411288 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 610366395 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 2477699501 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 436378814 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 330621598 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 99870091 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:UnblockCycles 54907489 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 180455810 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 168863429 # Number of cache lines fetched
+system.cpu.fetch.Cycles 400342229 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 931185 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 1404767222 # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles 49 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles 14936403 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.117758 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 168863429 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 169776992 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 0.916689 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 1532144387 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.666939 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.038798 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 499259849 32.89% 32.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 507370292 33.43% 66.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 273389808 18.01% 84.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 210662042 13.88% 98.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 8152383 0.54% 98.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1243560 0.08% 98.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 720 0.00% 98.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 8664 0.00% 98.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 17679635 1.16% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 1134818986 74.07% 74.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 25831687 1.69% 75.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 14383456 0.94% 76.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 13631087 0.89% 77.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 30570437 2.00% 79.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 20250642 1.32% 80.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 34285955 2.24% 83.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 37728615 2.46% 85.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 220643522 14.40% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1517766953 # Number of instructions fetched each cycle (Total)
-system.cpu.fp_regfile_reads 2 # number of floating regfile reads
-system.cpu.icache.ReadReq_accesses 129713560 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 37165.425532 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35455.808081 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 129712620 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 34935500 # number of ReadReq miss cycles
+system.cpu.fetch.rateDist::total 1532144387 # Number of instructions fetched each cycle (Total)
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system.cpu.icache.ReadReq_miss_rate 0.000007 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 940 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 148 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 28081000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 792 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_misses 1223 # number of ReadReq misses
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+system.cpu.icache.ReadReq_mshr_misses 867 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 163778.560606 # Average number of references to valid blocks.
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 129713560 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 37165.425532 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35455.808081 # average overall mshr miss latency
-system.cpu.icache.demand_hits 129712620 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 34935500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_accesses 168863429 # number of demand (read+write) accesses
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+system.cpu.icache.demand_avg_mshr_miss_latency 35310.841984 # average overall mshr miss latency
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+system.cpu.icache.demand_miss_latency 42445500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000007 # miss rate for demand accesses
-system.cpu.icache.demand_misses 940 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 148 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 28081000 # number of demand (read+write) MSHR miss cycles
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-system.cpu.icache.demand_mshr_misses 792 # number of demand (read+write) MSHR misses
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+system.cpu.icache.demand_mshr_hits 356 # number of demand (read+write) MSHR hits
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+system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 867 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.352940 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 722.820283 # Average occupied blocks per context
-system.cpu.icache.overall_accesses 129713560 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 37165.425532 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35455.808081 # average overall mshr miss latency
+system.cpu.icache.occ_%::0 0.386137 # Average percentage of cache occupancy
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 129712620 # number of overall hits
-system.cpu.icache.overall_miss_latency 34935500 # number of overall miss cycles
+system.cpu.icache.overall_hits 168862206 # number of overall hits
+system.cpu.icache.overall_miss_latency 42445500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000007 # miss rate for overall accesses
-system.cpu.icache.overall_misses 940 # number of overall misses
-system.cpu.icache.overall_mshr_hits 148 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 28081000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000006 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 792 # number of overall MSHR misses
+system.cpu.icache.overall_misses 1223 # number of overall misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 4 # number of replacements
-system.cpu.icache.sampled_refs 792 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 11 # number of replacements
+system.cpu.icache.sampled_refs 867 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 722.820283 # Cycle average of tags in use
-system.cpu.icache.total_refs 129712620 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 790.808810 # Cycle average of tags in use
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 214442 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 108628514 # Number of branches executed
+system.cpu.idleCycles 291024 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 111314295 # Number of branches executed
system.cpu.iew.EXEC:nop 0 # number of nop insts executed
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-system.cpu.iew.EXEC:refs 627755630 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 190105687 # Number of stores executed
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system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 1860684264 # num instructions consuming a value
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system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 1323598001 # num instructions producing a value
-system.cpu.iew.WB:rate 1.111847 # insts written-back per cycle
-system.cpu.iew.WB:sent 1688206003 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 6113342 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 1234561 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 466864036 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 67 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 3697894 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 198431314 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 1795988309 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 437649943 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 8316492 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 1690766136 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 11689 # Number of times the IQ has become full, causing a stall
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+system.cpu.iew.WB:sent 1842290775 # cumulative count of insts sent to commit
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+system.cpu.iew.iewBlockCycles 1415270 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 617903270 # Number of dispatched load instructions
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+system.cpu.iew.iewDispatchedInsts 2351086206 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 444791361 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 11969895 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 1843997360 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 60905 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 29266045 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 61051 # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 99870091 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 117847 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 29308 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 108968785 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 18692 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.cacheBlocked 29753 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 113796852 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 8470 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 6882405 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 14 # Number of loads that were rescheduled
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-system.cpu.iew.memOrderViolationEvents 6882405 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 2235 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 6111107 # Number of branches that were predicted taken incorrectly
-system.cpu.int_regfile_reads 3195299120 # number of integer regfile reads
-system.cpu.int_regfile_writes 1684589292 # number of integer regfile writes
-system.cpu.ipc 1.068191 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.068191 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0::No_OpClass 24153767 1.42% 1.42% # Type of FU issued
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-system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 62.78% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 62.78% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 62.78% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 62.78% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 62.78% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 62.78% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 62.78% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 62.78% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 62.78% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 62.78% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 62.78% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 62.78% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 62.78% # Type of FU issued
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-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 62.78% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 62.78% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 62.78% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 62.78% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 62.78% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 62.78% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 62.78% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 62.78% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 62.78% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 62.78% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead 442155303 26.02% 88.80% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite 190215801 11.20% 100.00% # Type of FU issued
+system.cpu.iew.lsq.thread.0.memOrderViolation 6921754 # Number of memory ordering violations
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+system.cpu.iew.lsq.thread.0.squashedLoads 198861145 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 62946497 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 6921754 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 3700861 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 4444875 # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads 3233304065 # number of integer regfile reads
+system.cpu.int_regfile_writes 1832324218 # number of integer regfile writes
+system.cpu.ipc 1.058116 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.058116 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0::No_OpClass 27128947 1.46% 1.46% # Type of FU issued
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+system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 65.41% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 65.41% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 65.41% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 65.41% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 65.41% # Type of FU issued
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+system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 65.41% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 65.41% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 65.41% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 65.41% # Type of FU issued
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+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 65.41% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 65.41% # Type of FU issued
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+system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 65.41% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 65.41% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 65.41% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 65.41% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 65.41% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead 450365179 24.27% 89.68% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite 191592240 10.32% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total 1699082628 # Type of FU issued
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-system.cpu.iq.ISSUE:fu_busy_rate 0.000529 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total 1855967255 # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt 4437489 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.002391 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu 2 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead 782842 87.13% 87.13% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite 115621 12.87% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu 118316 2.67% 2.67% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.67% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.67% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.67% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.67% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.67% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.67% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.67% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.67% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.67% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.67% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.67% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 2.67% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 2.67% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 2.67% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 2.67% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.67% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 2.67% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 2.67% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 2.67% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.67% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 2.67% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 2.67% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 2.67% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 2.67% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 2.67% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 2.67% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.67% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 2.67% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead 3486899 78.58% 81.24% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite 832274 18.76% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples 1517766953 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean 1.119462 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev 0.970342 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::samples 1532144387 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean 1.211353 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.177271 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0 418312841 27.56% 27.56% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1 673262157 44.36% 71.92% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2 290551111 19.14% 91.06% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3 102329684 6.74% 97.81% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4 29422654 1.94% 99.74% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5 3376155 0.22% 99.97% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6 428915 0.03% 99.99% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7 83172 0.01% 100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8 264 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0 466354124 30.44% 30.44% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1 601647548 39.27% 69.71% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2 244545222 15.96% 85.67% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3 139808763 9.13% 94.79% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4 60228260 3.93% 98.72% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5 13792665 0.90% 99.62% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6 4627487 0.30% 99.93% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7 960857 0.06% 99.99% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8 179461 0.01% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total 1517766953 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate 1.119304 # Inst issue rate
-system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
-system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes
-system.cpu.iq.int_alu_accesses 1675827322 # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads 4916833706 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses 1687762820 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes 1976960091 # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded 1795988242 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 1699082628 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 67 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 174090375 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 3040 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 322977188 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadExReq_accesses 247374 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34288.873379 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31083.636921 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits 188632 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency 2014197000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 0.237462 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 58742 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 1825915000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.237462 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 58742 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 207481 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34134.816432 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.350224 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 174959 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1110132500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.156747 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 32522 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1008356000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.156747 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 32522 # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 403776 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 403776 # number of Writeback hits
+system.cpu.iq.ISSUE:issued_per_cycle::total 1532144387 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate 1.211123 # Inst issue rate
+system.cpu.iq.fp_alu_accesses 18 # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads 33 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses 12 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes 32 # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses 1833275779 # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads 5248603279 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses 1839101554 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes 3087460502 # Number of integer instruction queue writes
+system.cpu.iq.iqInstsAdded 2351086128 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 1855967255 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 78 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 729454588 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 86926 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 28 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 1543114171 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadExReq_accesses 250094 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34363.888228 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31092.455043 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_hits 191260 # number of ReadExReq hits
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+system.cpu.l2cache.ReadExReq_miss_rate 0.235248 # miss rate for ReadExReq accesses
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+system.cpu.l2cache.ReadExReq_mshr_miss_latency 1829293500 # number of ReadExReq MSHR miss cycles
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+system.cpu.l2cache.ReadExReq_mshr_misses 58834 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 215648 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34134.880348 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.967489 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 182552 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 1129728000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.153472 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 33096 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1026173500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.153472 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 33096 # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 411288 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 411288 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 4.963363 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 5.099303 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 454855 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34233.975061 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31055.739393 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 363591 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 3124329500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.200644 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 91264 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 465742 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34281.442402 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31061.318394 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 373812 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 3151493000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.197384 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 91930 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 2834271000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.200644 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 91264 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 2855467000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.197384 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 91930 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.058891 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1 0.491980 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 1929.753834 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 16121.198217 # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses 454855 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34233.975061 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31055.739393 # average overall mshr miss latency
+system.cpu.l2cache.occ_%::0 0.059053 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.491352 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 1935.054426 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 16100.609355 # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses 465742 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34281.442402 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31061.318394 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 363591 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 3124329500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.200644 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 91264 # number of overall misses
+system.cpu.l2cache.overall_hits 373812 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 3151493000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.197384 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 91930 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 2834271000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.200644 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 91264 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 2855467000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.197384 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 91930 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 72998 # number of replacements
-system.cpu.l2cache.sampled_refs 88598 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 73661 # number of replacements
+system.cpu.l2cache.sampled_refs 89262 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 18050.952051 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 439744 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 18035.663781 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 455174 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 58419 # number of writebacks
-system.cpu.memDep0.conflictingLoads 312249439 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 119901234 # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads 466864036 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 198431314 # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads 865536711 # number of misc regfile reads
-system.cpu.numCycles 1517981395 # number of cpu cycles simulated
+system.cpu.l2cache.writebacks 58542 # number of writebacks
+system.cpu.memDep0.conflictingLoads 537232404 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 219207458 # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads 617903270 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 251132554 # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads 931505074 # number of misc regfile reads
+system.cpu.numCycles 1532435411 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles 28986025 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:BlockCycles 175534951 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1617994650 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 33672472 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 389992916 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 45640252 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents 23 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 4455391031 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 1827559293 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 1825935922 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 951399892 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 29266045 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 118119949 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 207941272 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups 32 # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups 4455390999 # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles 2126 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 68 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 172417007 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 68 # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads 3280069639 # The number of ROB reads
-system.cpu.rob.rob_writes 3621261017 # The number of ROB writes
-system.cpu.timesIdled 45168 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:IQFullEvents 318243703 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 499996104 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 107154792 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 44 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 5827367622 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 2403532061 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 2403383901 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 306300874 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 99870091 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 450439326 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 785389251 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups 96 # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups 5827367526 # Number of integer rename lookups
+system.cpu.rename.RENAME:serializeStallCycles 3041 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 87 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 739921776 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 87 # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads 3775835718 # The number of ROB reads
+system.cpu.rob.rob_writes 4802062478 # The number of ROB writes
+system.cpu.timesIdled 45517 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
---------- End Simulation Statistics ----------
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
-cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing
+cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing
egid=100
env=
errout=cerr
All Rights Reserved
-M5 compiled Feb 8 2011 00:58:32
-M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip
-M5 started Feb 8 2011 00:58:34
+M5 compiled Feb 12 2011 02:22:23
+M5 revision 5e76f9de6972 7961 default qtip tip x86branchdetectstats.patch
+M5 started Feb 12 2011 02:22:27
M5 executing on burrito
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/o3-timing
+command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 137353348000 because target called exit()
+Exiting @ tick 98622214000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 205513 # Simulator instruction rate (inst/s)
-host_mem_usage 367352 # Number of bytes of host memory used
-host_seconds 1353.65 # Real time elapsed on the host
-host_tick_rate 101468739 # Simulator tick rate (ticks/s)
+host_inst_rate 133029 # Simulator instruction rate (inst/s)
+host_mem_usage 371192 # Number of bytes of host memory used
+host_seconds 2091.22 # Real time elapsed on the host
+host_tick_rate 47160241 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 278192519 # Number of instructions simulated
-sim_seconds 0.137353 # Number of seconds simulated
-sim_ticks 137353348000 # Number of ticks simulated
+sim_seconds 0.098622 # Number of seconds simulated
+sim_ticks 98622214000 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 43044448 # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 43605632 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 44152407 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 44769192 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect 4328985 # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 43605708 # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 43605708 # Number of BP lookups
+system.cpu.BPredUnit.condIncorrect 3292099 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 50608102 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 50608102 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 29309710 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 2295915 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 11603540 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 264042401 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean 1.053590 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev 1.542507 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 176948364 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 1.572168 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 2.280995 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 131063071 49.64% 49.64% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1 68068160 25.78% 75.42% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2 28810036 10.91% 86.33% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3 19729094 7.47% 93.80% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4 3997193 1.51% 95.31% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5 3201909 1.21% 96.53% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6 5187793 1.96% 98.49% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7 1689230 0.64% 99.13% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 2295915 0.87% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 83964580 47.45% 47.45% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 36146762 20.43% 67.88% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 16087394 9.09% 76.97% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 14069173 7.95% 84.92% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 7224288 4.08% 89.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 2649535 1.50% 90.50% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 3731341 2.11% 92.61% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 1471751 0.83% 93.44% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 11603540 6.56% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 264042401 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 176948364 # Number of insts commited each cycle
system.cpu.commit.COM:count 278192519 # Number of instructions committed
system.cpu.commit.COM:fp_insts 40 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 122219139 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 4328993 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 3292117 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 278192519 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 61447181 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 130955012 # The number of squashed insts skipped by commit
system.cpu.committedInsts 278192519 # Number of Instructions Simulated
system.cpu.committedInsts_total 278192519 # Number of Instructions Simulated
-system.cpu.cpi 0.987470 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.987470 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 78473515 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 5892.080019 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2802.465298 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 76426591 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 12060640000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.026084 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 2046924 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 76655 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 5521610500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.025107 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 1970269 # number of ReadReq MSHR misses
+system.cpu.cpi 0.709021 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.709021 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 69458873 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 6142.707591 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3039.983703 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 67343989 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 12991114000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.030448 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 2114884 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 142693 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 5995428500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.028394 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 1972191 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 21791.452056 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 16914.293943 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 31282890 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 3418228961 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.004989 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 156861 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 50497 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 1799071961 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.003383 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 106364 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 3035.211268 # average number of cycles each access was blocked
+system.cpu.dcache.WriteReq_avg_miss_latency 17842.235128 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17696.947420 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 31210017 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 4098968045 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.007307 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 229734 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 123609 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 1878088545 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.003376 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 106125 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 3358.823529 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 51.867365 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 71 # number of cycles access was blocked
+system.cpu.dcache.avg_refs 47.420176 # Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs 85 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 215500 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 285500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 109913266 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 7023.765459 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 3525.265399 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 107709481 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 15478868961 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.020050 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 2203785 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 127152 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 7320682461 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.018893 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 2076633 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 100898624 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 7289.068857 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 3788.411890 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 98554006 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 17090082045 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.023237 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 2344618 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 266302 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 7873517045 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.020598 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 2078316 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.994785 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4074.637859 # Average occupied blocks per context
-system.cpu.dcache.overall_accesses 109913266 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 7023.765459 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 3525.265399 # average overall mshr miss latency
+system.cpu.dcache.occ_%::0 0.994974 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4075.414607 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses 100898624 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 7289.068857 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 3788.411890 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 107709481 # number of overall hits
-system.cpu.dcache.overall_miss_latency 15478868961 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.020050 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 2203785 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 127152 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 7320682461 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.018893 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 2076633 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 98554006 # number of overall hits
+system.cpu.dcache.overall_miss_latency 17090082045 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.023237 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 2344618 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 266302 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 7873517045 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.020598 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 2078316 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 2072537 # number of replacements
-system.cpu.dcache.sampled_refs 2076633 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 2074218 # number of replacements
+system.cpu.dcache.sampled_refs 2078314 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4074.637859 # Cycle average of tags in use
-system.cpu.dcache.total_refs 107709481 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 54571641000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 1440067 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 1078320 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts 365035506 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 68035567 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 194761019 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 10324266 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles 167495 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 43605708 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 29060081 # Number of cache lines fetched
-system.cpu.fetch.Cycles 205057262 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 469074 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 209709437 # Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles 11 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles 4648806 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.158736 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 29060081 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 43044448 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 0.763394 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 274366667 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.362439 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 1.220161 # Number of instructions fetched each cycle (Total)
+system.cpu.dcache.tagsinuse 4075.414607 # Cycle average of tags in use
+system.cpu.dcache.total_refs 98554015 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 40655663000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 1442059 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 21837286 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 443283148 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 77587406 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 75762450 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 19022168 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:UnblockCycles 1761222 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 50608102 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 34652495 # Number of cache lines fetched
+system.cpu.fetch.Cycles 82344495 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 326035 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 259681215 # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles 35 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles 3883025 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.256576 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 34652495 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 44152407 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.316545 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 195970532 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.323843 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.188074 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 75544313 27.53% 27.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 99907030 36.41% 63.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 38310109 13.96% 77.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 50324165 18.34% 96.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 5339949 1.95% 98.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 4719664 1.72% 99.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 210294 0.08% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 928 0.00% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 10215 0.00% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 116145210 59.27% 59.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 6750085 3.44% 62.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 3016102 1.54% 64.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 8362073 4.27% 68.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 7646936 3.90% 72.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 6348764 3.24% 75.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 9080088 4.63% 80.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 8246058 4.21% 84.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 30375216 15.50% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 274366667 # Number of instructions fetched each cycle (Total)
-system.cpu.fp_regfile_reads 46 # number of floating regfile reads
-system.cpu.fp_regfile_writes 32 # number of floating regfile writes
-system.cpu.icache.ReadReq_accesses 29060081 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 37083.333333 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35353.296703 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 29059007 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 39827500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000037 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 1074 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 164 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 32171500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000031 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 910 # number of ReadReq MSHR misses
+system.cpu.fetch.rateDist::total 195970532 # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads 75 # number of floating regfile reads
+system.cpu.fp_regfile_writes 41 # number of floating regfile writes
+system.cpu.icache.ReadReq_accesses 34652495 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 35675.242356 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 35201.684836 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 34651154 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 47840500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000039 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 1341 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 332 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 35518500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000029 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 1009 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 31932.974725 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 34376.144841 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 29060081 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 37083.333333 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35353.296703 # average overall mshr miss latency
-system.cpu.icache.demand_hits 29059007 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 39827500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000037 # miss rate for demand accesses
-system.cpu.icache.demand_misses 1074 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 164 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 32171500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000031 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 910 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses 34652495 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 35675.242356 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 35201.684836 # average overall mshr miss latency
+system.cpu.icache.demand_hits 34651154 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 47840500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000039 # miss rate for demand accesses
+system.cpu.icache.demand_misses 1341 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 332 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 35518500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000029 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 1009 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.357987 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 733.158070 # Average occupied blocks per context
-system.cpu.icache.overall_accesses 29060081 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 37083.333333 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35353.296703 # average overall mshr miss latency
+system.cpu.icache.occ_%::0 0.392466 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 803.770978 # Average occupied blocks per context
+system.cpu.icache.overall_accesses 34652495 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 35675.242356 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 35201.684836 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 29059007 # number of overall hits
-system.cpu.icache.overall_miss_latency 39827500 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000037 # miss rate for overall accesses
-system.cpu.icache.overall_misses 1074 # number of overall misses
-system.cpu.icache.overall_mshr_hits 164 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 32171500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000031 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 910 # number of overall MSHR misses
+system.cpu.icache.overall_hits 34651154 # number of overall hits
+system.cpu.icache.overall_miss_latency 47840500 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000039 # miss rate for overall accesses
+system.cpu.icache.overall_misses 1341 # number of overall misses
+system.cpu.icache.overall_mshr_hits 332 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 35518500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000029 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 1009 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 37 # number of replacements
-system.cpu.icache.sampled_refs 910 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 60 # number of replacements
+system.cpu.icache.sampled_refs 1008 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 733.158070 # Cycle average of tags in use
-system.cpu.icache.total_refs 29059007 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 803.770978 # Cycle average of tags in use
+system.cpu.icache.total_refs 34651154 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 340030 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 31975279 # Number of branches executed
+system.cpu.idleCycles 1273897 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 33755681 # Number of branches executed
system.cpu.iew.EXEC:nop 0 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.141834 # Inst execution rate
-system.cpu.iew.EXEC:refs 137788104 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 32893684 # Number of stores executed
+system.cpu.iew.EXEC:rate 1.719732 # Inst execution rate
+system.cpu.iew.EXEC:refs 143271490 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 33964004 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 268477654 # num instructions consuming a value
-system.cpu.iew.WB:count 310858537 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.831176 # average fanout of values written-back
+system.cpu.iew.WB:consumers 356152066 # num instructions consuming a value
+system.cpu.iew.WB:count 334303723 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.713943 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 223152216 # num instructions producing a value
-system.cpu.iew.WB:rate 1.131602 # insts written-back per cycle
-system.cpu.iew.WB:sent 311298125 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 5432801 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 434257 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 113153901 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 453 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 3329994 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 36225707 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 339638144 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 104894420 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 7540683 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 313669330 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 1132 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers 254272214 # num instructions producing a value
+system.cpu.iew.WB:rate 1.694870 # insts written-back per cycle
+system.cpu.iew.WB:sent 336664522 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 3987132 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 754395 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 138835558 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 663120 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 42750154 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 409142439 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 109307486 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 6572046 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 339207523 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 2275 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 39972 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 10324266 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 75875 # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents 78833 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 19022168 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 104797 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 6157 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 26233968 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 75546 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.cacheBlocked 14565 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 39666706 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 30063 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 373621 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 2668 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 22374513 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 4785956 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 373621 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 7861 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 5424940 # Number of branches that were predicted taken incorrectly
-system.cpu.int_regfile_reads 553724199 # number of integer regfile reads
-system.cpu.int_regfile_writes 279097661 # number of integer regfile writes
-system.cpu.ipc 1.012689 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.012689 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0::No_OpClass 16700 0.01% 0.01% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu 181103840 56.38% 56.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 56.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 56.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd 15 0.00% 56.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 56.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 56.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 56.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 56.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 56.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 56.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 56.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 56.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 56.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 56.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 56.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 56.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 56.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 56.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 56.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 56.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 56.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 56.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 56.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 56.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 56.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 56.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 56.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 56.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 56.39% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead 106927667 33.29% 89.68% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite 33161791 10.32% 100.00% # Type of FU issued
+system.cpu.iew.lsq.thread.0.memOrderViolation 1469253 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 2742 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 48056170 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 11310403 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 1469253 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 865481 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 3121651 # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads 577634708 # number of integer regfile reads
+system.cpu.int_regfile_writes 302216415 # number of integer regfile writes
+system.cpu.ipc 1.410395 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.410395 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0::No_OpClass 16702 0.00% 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu 200471700 57.98% 57.98% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 57.98% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 57.98% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd 15 0.00% 57.98% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 57.98% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 57.98% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 57.98% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 57.98% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 57.98% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 57.98% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 57.98% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 57.98% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 57.98% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 57.98% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 57.98% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 57.98% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 57.98% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 57.98% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 57.98% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 57.98% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 57.98% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 57.98% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 57.98% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 57.98% # Type of FU issued
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+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 57.98% # Type of FU issued
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+system.cpu.iq.ISSUE:FU_type_0::MemRead 110857049 32.06% 90.04% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite 34434103 9.96% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total 321210013 # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt 1288241 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.004011 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total 345779569 # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt 4109732 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.011885 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu 1 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead 1088765 84.52% 84.52% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite 199475 15.48% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu 26819 0.65% 0.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.65% # attempts to use FU when none available
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+system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.65% # attempts to use FU when none available
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+system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.65% # attempts to use FU when none available
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+system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.65% # attempts to use FU when none available
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+system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.65% # attempts to use FU when none available
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+system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.65% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead 3817756 92.90% 93.55% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite 265157 6.45% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples 274366667 # Number of insts issued each cycle
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-system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.057250 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::samples 195970532 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean 1.764447 # Number of insts issued each cycle
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system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0 85009751 30.98% 30.98% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1 94999011 34.62% 65.61% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2 64668868 23.57% 89.18% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3 24623631 8.97% 98.15% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4 3181639 1.16% 99.31% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5 1035626 0.38% 99.69% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6 839375 0.31% 100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7 8691 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8 75 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0 63955785 32.64% 32.64% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1 38956843 19.88% 52.51% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2 30997952 15.82% 68.33% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3 27554899 14.06% 82.39% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4 19728653 10.07% 92.46% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5 8783605 4.48% 96.94% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6 3191043 1.63% 98.57% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7 2230786 1.14% 99.71% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8 570966 0.29% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total 274366667 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate 1.169284 # Inst issue rate
-system.cpu.iq.fp_alu_accesses 58 # Number of floating point alu accesses
-system.cpu.iq.fp_inst_queue_reads 116 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_wakeup_accesses 52 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_writes 102 # Number of floating instruction queue writes
-system.cpu.iq.int_alu_accesses 322481496 # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads 918075310 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses 310858485 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes 400954774 # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded 339637691 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 321210013 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 453 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 61001038 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 492 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 74571352 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadExReq_accesses 106364 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34222.852226 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31038.534987 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits 63948 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency 1451596500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 0.398782 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 42416 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 1316530500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.398782 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 42416 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 1971179 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34221.265286 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31012.315915 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 1936752 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1178135500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.017465 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 34427 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1067661000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017465 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 34427 # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 1440067 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 1440067 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs 1272.727273 # average number of cycles each access was blocked
+system.cpu.iq.ISSUE:issued_per_cycle::total 195970532 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate 1.753051 # Inst issue rate
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+system.cpu.iq.fp_inst_queue_reads 224 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses 83 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes 263 # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses 349872489 # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads 891669703 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses 334303640 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes 540919004 # Number of integer instruction queue writes
+system.cpu.iq.iqInstsAdded 409141974 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 345779569 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 465 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 130872312 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 30525 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 19 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 221868127 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadExReq_accesses 106126 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34139.167845 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31050.412541 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_hits 63706 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency 1448183500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 0.399714 # miss rate for ReadExReq accesses
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+system.cpu.l2cache.ReadExReq_mshr_miss_latency 1317158500 # number of ReadExReq MSHR miss cycles
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+system.cpu.l2cache.ReadReq_accesses 1973197 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34279.521718 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31013.978995 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 1938824 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 1178290000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.017420 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 34373 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1066043500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017420 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 34373 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 1442058 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 1442058 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2176.470588 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 42.754105 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs 11 # number of cycles access was blocked
+system.cpu.l2cache.avg_refs 42.835533 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked::no_mshrs 17 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_mshrs 14000 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_mshrs 37000 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 2077543 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34222.141249 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31026.788387 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 2000700 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 2629732000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.036987 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 76843 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 2079323 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34201.991067 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31034.104671 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 2002530 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 2626473500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.036932 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 76793 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 2384191500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.036987 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 76843 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 2383202000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.036932 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 76793 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.188685 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1 0.343727 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 6182.815069 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 11263.234870 # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses 2077543 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34222.141249 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31026.788387 # average overall mshr miss latency
+system.cpu.l2cache.occ_%::0 0.185144 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.337522 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 6066.784489 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 11059.931141 # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses 2079323 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34201.991067 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31034.104671 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 2000700 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 2629732000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.036987 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 76843 # number of overall misses
+system.cpu.l2cache.overall_hits 2002530 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 2626473500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.036932 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 76793 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 2384191500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.036987 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 76843 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 2383202000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.036932 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 76793 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 49399 # number of replacements
-system.cpu.l2cache.sampled_refs 77399 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 49342 # number of replacements
+system.cpu.l2cache.sampled_refs 77347 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 17446.049939 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 3309125 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 17126.715630 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 3313200 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 29483 # number of writebacks
-system.cpu.memDep0.conflictingLoads 30510087 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 6437799 # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads 113153901 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 36225707 # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads 204124363 # number of misc regfile reads
-system.cpu.numCycles 274706697 # number of cpu cycles simulated
+system.cpu.l2cache.writebacks 29450 # number of writebacks
+system.cpu.memDep0.conflictingLoads 87882428 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 16100005 # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads 138835558 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 42750154 # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads 218323859 # number of misc regfile reads
+system.cpu.numCycles 197244429 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles 682912 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:BlockCycles 6557218 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 248344192 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 11638 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 72242818 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 253088 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 867316457 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 357042681 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 317208618 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 190696526 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 10324266 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 414923 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 68864426 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups 276 # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups 867316181 # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles 5222 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 452 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 585103 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 450 # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads 601386186 # The number of ROB reads
-system.cpu.rob.rob_writes 689603687 # The number of ROB writes
-system.cpu.timesIdled 20021 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:IQFullEvents 228138 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 83203716 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 14824029 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 13 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 1059543178 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 431467970 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 388798641 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 71280917 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 19022168 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 15900092 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 140454449 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups 574 # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups 1059542604 # Number of integer rename lookups
+system.cpu.rename.RENAME:serializeStallCycles 6421 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 469 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 38067869 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 463 # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads 574492355 # The number of ROB reads
+system.cpu.rob.rob_writes 837321831 # The number of ROB writes
+system.cpu.timesIdled 40675 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 444 # Number of system calls
---------- End Simulation Statistics ----------
All Rights Reserved
-M5 compiled Feb 10 2011 23:58:37
-M5 revision a36c6a370231 7943 default qtip resforflagsstats.patch tip
-M5 started Feb 10 2011 23:58:40
+M5 compiled Feb 12 2011 02:22:23
+M5 revision 5e76f9de6972 7961 default qtip tip x86branchdetectstats.patch
+M5 started Feb 12 2011 02:22:27
M5 executing on burrito
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
- Reading the dictionary files: *****************************info: Increasing stack size by one page.
-********************
+ Reading the dictionary files: ***********************info: Increasing stack size by one page.
+**************************
58924 words stored in 3784810 bytes
Echoing of input sentence turned on.
* as had expected the party to be a success , it was a success
-info: Increasing stack size by one page.
* do you know where John 's
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
info: Increasing stack size by one page.
+info: Increasing stack size by one page.
* how fast the program is it
* I am wondering whether to invite to the party
* I gave him for his birthday it
about 2 million people attended
the five best costumes got prizes
No errors!
-Exiting @ tick 698491025500 because target called exit()
+Exiting @ tick 610952992000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 139548 # Simulator instruction rate (inst/s)
-host_mem_usage 244652 # Number of bytes of host memory used
-host_seconds 10956.69 # Real time elapsed on the host
-host_tick_rate 63750196 # Simulator tick rate (ticks/s)
+host_inst_rate 130186 # Simulator instruction rate (inst/s)
+host_mem_usage 285488 # Number of bytes of host memory used
+host_seconds 11733.03 # Real time elapsed on the host
+host_tick_rate 52071207 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1528988756 # Number of instructions simulated
-sim_seconds 0.698491 # Number of seconds simulated
-sim_ticks 698491025500 # Number of ticks simulated
+sim_insts 1527476062 # Number of instructions simulated
+sim_seconds 0.610953 # Number of seconds simulated
+sim_ticks 610952992000 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 172887264 # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 187312240 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 220273443 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 239822696 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect 17887438 # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 187888188 # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 187888188 # Number of BP lookups
+system.cpu.BPredUnit.condIncorrect 16691862 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 254901320 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 254901320 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches 149758588 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 10029766 # number cycles where commit BW limit reached
+system.cpu.commit.COM:branches 149616585 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 33918821 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 1350871673 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean 1.131853 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev 1.433209 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 1083369873 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 1.409930 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 1.877801 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 568349245 42.07% 42.07% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1 413717350 30.63% 72.70% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2 172321570 12.76% 85.46% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3 110104358 8.15% 93.61% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4 43035291 3.19% 96.79% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5 18507275 1.37% 98.16% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6 8248201 0.61% 98.77% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7 6558617 0.49% 99.26% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 10029766 0.74% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 454928288 41.99% 41.99% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 282557908 26.08% 68.07% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 120287774 11.10% 79.18% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 105365409 9.73% 88.90% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 40172301 3.71% 92.61% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 27676804 2.55% 95.16% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 11415389 1.05% 96.22% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 7047179 0.65% 96.87% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 33918821 3.13% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 1350871673 # Number of insts commited each cycle
-system.cpu.commit.COM:count 1528988756 # Number of instructions committed
+system.cpu.commit.COM:committed_per_cycle::total 1083369873 # Number of insts commited each cycle
+system.cpu.commit.COM:count 1527476062 # Number of instructions committed
system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
-system.cpu.commit.COM:int_insts 1528317614 # Number of committed integer instructions.
-system.cpu.commit.COM:loads 384102160 # Number of loads committed
+system.cpu.commit.COM:int_insts 1526804920 # Number of committed integer instructions.
+system.cpu.commit.COM:loads 383724495 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 533262345 # Number of memory references committed
+system.cpu.commit.COM:refs 532790180 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 17888761 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 1528988756 # The number of committed instructions
+system.cpu.commit.branchMispredicts 16726957 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 1527476062 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 257046446 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 1528988756 # Number of Instructions Simulated
-system.cpu.committedInsts_total 1528988756 # Number of Instructions Simulated
-system.cpu.cpi 0.913664 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.913664 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 334229227 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 14263.584813 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8537.168964 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 332171764 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 29346798000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.006156 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 2057463 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 319131 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 14840434000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.005201 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 1738332 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 16290.992476 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12654.921756 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 148197195 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 15688323500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.006456 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 963006 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 176041 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 9958980500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.005276 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 786965 # number of WriteReq MSHR misses
+system.cpu.commit.commitSquashedInsts 841443918 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 1527476062 # Number of Instructions Simulated
+system.cpu.committedInsts_total 1527476062 # Number of Instructions Simulated
+system.cpu.cpi 0.799951 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.799951 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 320046346 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 15794.070061 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8150.695480 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 317137092 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 45948961500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.009090 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 2909254 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 1183970 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 14062264500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.005391 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 1725284 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 149065701 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 23554.108597 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 18051.470496 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 147419835 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 38766906500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.011041 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 1645866 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 608291 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 18729754500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.006961 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 1037575 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 190.400689 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 185.704246 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 483389428 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 14909.976398 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 9820.395185 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 480368959 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 45035121500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.006249 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 3020469 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 495172 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 24799414500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.005224 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 2525297 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 469112047 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 18597.944291 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 11868.871701 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 464556927 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 84715868000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.009710 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 4555120 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 1792261 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 32792019000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.005890 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 2762859 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.997741 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4086.747665 # Average occupied blocks per context
-system.cpu.dcache.overall_accesses 483389428 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 14909.976398 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 9820.395185 # average overall mshr miss latency
+system.cpu.dcache.occ_%::0 0.998028 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4087.922333 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses 469112047 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 18597.944291 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 11868.871701 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 480368959 # number of overall hits
-system.cpu.dcache.overall_miss_latency 45035121500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.006249 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 3020469 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 495172 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 24799414500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.005224 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 2525297 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 464556927 # number of overall hits
+system.cpu.dcache.overall_miss_latency 84715868000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.009710 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 4555120 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 1792261 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 32792019000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.005890 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 2762859 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 2518885 # number of replacements
-system.cpu.dcache.sampled_refs 2522981 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 2504740 # number of replacements
+system.cpu.dcache.sampled_refs 2508836 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4086.747665 # Cycle average of tags in use
-system.cpu.dcache.total_refs 480377321 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 3312879000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 2225275 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 18280435 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts 1869219380 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 343093281 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 984893533 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 39316255 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles 4604424 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 187888188 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 144979108 # Number of cache lines fetched
-system.cpu.fetch.Cycles 1039380252 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 2070461 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 999560833 # Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles 1828 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles 17988626 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.134496 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 144979108 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 172887264 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 0.715514 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 1390187928 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.363495 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 1.275570 # Number of instructions fetched each cycle (Total)
+system.cpu.dcache.tagsinuse 4087.922333 # Cycle average of tags in use
+system.cpu.dcache.total_refs 465901497 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 2529382000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 2229751 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 215366555 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 2516935544 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 437043857 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 404205746 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 113949773 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:UnblockCycles 26753715 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 254901320 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 190461812 # Number of cache lines fetched
+system.cpu.fetch.Cycles 445534669 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 3068431 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 1374706338 # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles 85274 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles 18549281 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.208610 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 190461812 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 220273443 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.125051 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 1197319646 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.144693 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.178811 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 388271402 27.93% 27.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 493387093 35.49% 63.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 229970387 16.54% 79.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 224046516 16.12% 96.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 21915192 1.58% 97.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 25802023 1.86% 99.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 493192 0.04% 99.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 12 0.00% 99.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 6302111 0.45% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 756027205 63.14% 63.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 34054494 2.84% 65.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 36745231 3.07% 69.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 33767076 2.82% 71.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 21459245 1.79% 73.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 40493114 3.38% 77.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 45860411 3.83% 80.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 35731624 2.98% 83.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 193181246 16.13% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1390187928 # Number of instructions fetched each cycle (Total)
-system.cpu.fp_regfile_reads 9 # number of floating regfile reads
-system.cpu.icache.ReadReq_accesses 144979108 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 22807.726664 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 19441.756997 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 144972391 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 153199500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000046 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 6717 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 536 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 120169500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000043 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 6181 # number of ReadReq MSHR misses
+system.cpu.fetch.rateDist::total 1197319646 # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads 31 # number of floating regfile reads
+system.cpu.icache.ReadReq_accesses 190461812 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 6527.954910 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 3419.281975 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 190192396 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 1758735500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.001415 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 269416 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 1570 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 915841000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.001406 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 267846 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 43679.520036 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 17699.832480 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 144979108 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 22807.726664 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 19441.756997 # average overall mshr miss latency
-system.cpu.icache.demand_hits 144972391 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 153199500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000046 # miss rate for demand accesses
-system.cpu.icache.demand_misses 6717 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 536 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 120169500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000043 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 6181 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses 190461812 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 6527.954910 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 3419.281975 # average overall mshr miss latency
+system.cpu.icache.demand_hits 190192396 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 1758735500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.001415 # miss rate for demand accesses
+system.cpu.icache.demand_misses 269416 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 1570 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 915841000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.001406 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 267846 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.450710 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 923.054085 # Average occupied blocks per context
-system.cpu.icache.overall_accesses 144979108 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 22807.726664 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 19441.756997 # average overall mshr miss latency
+system.cpu.icache.occ_%::0 0.466021 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 954.411836 # Average occupied blocks per context
+system.cpu.icache.overall_accesses 190461812 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 6527.954910 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 3419.281975 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 144972391 # number of overall hits
-system.cpu.icache.overall_miss_latency 153199500 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000046 # miss rate for overall accesses
-system.cpu.icache.overall_misses 6717 # number of overall misses
-system.cpu.icache.overall_mshr_hits 536 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 120169500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000043 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 6181 # number of overall MSHR misses
+system.cpu.icache.overall_hits 190192396 # number of overall hits
+system.cpu.icache.overall_miss_latency 1758735500 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.001415 # miss rate for overall accesses
+system.cpu.icache.overall_misses 269416 # number of overall misses
+system.cpu.icache.overall_mshr_hits 1570 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 915841000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.001406 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 267846 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 1737 # number of replacements
-system.cpu.icache.sampled_refs 3319 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 9298 # number of replacements
+system.cpu.icache.sampled_refs 10745 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 923.054085 # Cycle average of tags in use
-system.cpu.icache.total_refs 144972327 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 954.411836 # Cycle average of tags in use
+system.cpu.icache.total_refs 190184700 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 6794124 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 154306305 # Number of branches executed
+system.cpu.icache.writebacks 3 # number of writebacks
+system.cpu.idleCycles 24586339 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 175611349 # Number of branches executed
system.cpu.iew.EXEC:nop 0 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.173655 # Inst execution rate
-system.cpu.iew.EXEC:refs 571924541 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 156120222 # Number of stores executed
+system.cpu.iew.EXEC:rate 1.537639 # Inst execution rate
+system.cpu.iew.EXEC:refs 604612823 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 164362000 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 1557537154 # num instructions consuming a value
-system.cpu.iew.WB:count 1628444279 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.759406 # average fanout of values written-back
+system.cpu.iew.WB:consumers 2150205320 # num instructions consuming a value
+system.cpu.iew.WB:count 1865910107 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.666196 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 1182802327 # num instructions producing a value
-system.cpu.iew.WB:rate 1.165687 # insts written-back per cycle
-system.cpu.iew.WB:sent 1630313962 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 18753816 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 4588629 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 454402470 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 570 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 11948307 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 170547501 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 1786034876 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 415804319 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 21119599 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 1639574511 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 357621 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers 1432458045 # num instructions producing a value
+system.cpu.iew.WB:rate 1.527049 # insts written-back per cycle
+system.cpu.iew.WB:sent 1872952311 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 18187438 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 9702727 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 598780500 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 6555 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 2427132 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 227725972 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 2368916953 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 440250823 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 24902522 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 1878850199 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 999062 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 9695 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 39316255 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 668139 # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents 48995 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 113949773 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 1501929 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 80610216 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 294173 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.forwLoads 119150872 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 153037 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 154646 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 837 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 70300310 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 21387316 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 154646 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 515713 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 18238103 # Number of branches that were predicted taken incorrectly
-system.cpu.int_regfile_reads 2891828761 # number of integer regfile reads
-system.cpu.int_regfile_writes 1524435086 # number of integer regfile writes
-system.cpu.ipc 1.094494 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.094494 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0::No_OpClass 1929805 0.12% 0.12% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu 1078730229 64.96% 65.07% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 65.07% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 65.07% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 65.07% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 65.07% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 65.07% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 65.07% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 65.07% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 65.07% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 65.07% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 65.07% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 65.07% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 65.07% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 65.07% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 65.07% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 65.07% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 65.07% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 65.07% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 65.07% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 65.07% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 65.07% # Type of FU issued
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-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 65.07% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 65.07% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 65.07% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 65.07% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 65.07% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 65.07% # Type of FU issued
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-system.cpu.iq.ISSUE:FU_type_0::MemWrite 158763559 9.56% 100.00% # Type of FU issued
+system.cpu.iew.lsq.thread.0.memOrderViolation 1905759 # Number of memory ordering violations
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+system.cpu.iew.lsq.thread.0.squashedLoads 215056005 # Number of loads squashed
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+system.cpu.iew.memOrderViolationEvents 1905759 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 2718790 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 15468648 # Number of branches that were predicted taken incorrectly
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+system.cpu.ipc 1.250077 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.250077 # IPC: Total IPC of All Threads
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system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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-system.cpu.iq.ISSUE:issued_per_cycle::3 117467117 8.45% 96.94% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4 33024815 2.38% 99.31% # Number of insts issued each cycle
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+system.cpu.iq.ISSUE:issued_per_cycle::1 297509781 24.85% 56.63% # Number of insts issued each cycle
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system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
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-system.cpu.iq.ISSUE:rate 1.188773 # Inst issue rate
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-system.cpu.iq.iqInstsIssued 1660694110 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 570 # Number of non-speculative instructions added to the IQ
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-system.cpu.iq.iqSquashedInstsIssued 30635 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 443519402 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadExReq_accesses 789066 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34257.778038 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31001.587520 # average ReadExReq mshr miss latency
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-system.cpu.l2cache.ReadExReq_mshr_miss_latency 7674629000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.313733 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 247556 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 1737232 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34158.153227 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.616867 # average ReadReq mshr miss latency
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-system.cpu.l2cache.ReadReq_miss_latency 11388806500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.191923 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 333414 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 10336706500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191923 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 333414 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 2858 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 24.740050 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000.358551 # average UpgradeReq mshr miss latency
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-system.cpu.l2cache.UpgradeReq_miss_latency 69000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 0.975857 # miss rate for UpgradeReq accesses
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-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 86460000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.975857 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 2789 # number of UpgradeReq MSHR misses
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-system.cpu.l2cache.Writeback_hits 2225275 # number of Writeback hits
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+system.cpu.iq.iqSquashedInstsIssued 555850 # Number of squashed instructions issued
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+system.cpu.l2cache.ReadReq_avg_miss_latency 34171.480760 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.917505 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 1415970 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 10822415500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.182786 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 316709 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 9818903000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.182786 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 316709 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 256943 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 40.077896 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31003.030576 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_hits 1216 # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_miss_latency 10249000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_rate 0.995267 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_misses 255727 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 7928312000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.995267 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_misses 255727 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 2229754 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 2229754 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 5.353417 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 5.404070 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 2526298 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34200.604162 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31002.178254 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 1945328 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 19869525000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.229969 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 580970 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 2519527 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34208.290090 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31002.276142 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 1955854 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 19282289500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.223722 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 563673 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 18011335500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.229969 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 580970 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 17475146000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.223722 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 563673 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.234251 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1 0.418210 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 7675.941579 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 13703.908999 # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses 2526298 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34200.604162 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31002.178254 # average overall mshr miss latency
+system.cpu.l2cache.occ_%::0 0.213694 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.433705 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 7002.339473 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 14211.631717 # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses 2519527 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34208.290090 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31002.276142 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 1945328 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 19869525000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.229969 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 580970 # number of overall misses
+system.cpu.l2cache.overall_hits 1955854 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 19282289500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.223722 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 563673 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 18011335500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.229969 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 580970 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 17475146000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.223722 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 563673 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 570217 # number of replacements
-system.cpu.l2cache.sampled_refs 589293 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 553099 # number of replacements
+system.cpu.l2cache.sampled_refs 571950 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 21379.850577 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 3154731 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 377230361000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 411577 # number of writebacks
-system.cpu.memDep0.conflictingLoads 169465698 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 40622935 # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads 454402470 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 170547499 # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads 909615360 # number of misc regfile reads
-system.cpu.numCycles 1396982052 # number of cpu cycles simulated
+system.cpu.l2cache.tagsinuse 21213.971190 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 3090858 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 329890014000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 404346 # number of writebacks
+system.cpu.memDep0.conflictingLoads 432040536 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 167867809 # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads 598780500 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 227724252 # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads 1024928879 # number of misc regfile reads
+system.cpu.numCycles 1221905985 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles 7556367 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 1427299027 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 5884693 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 361176398 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 2156935 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents 61 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 4360508954 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 1840516856 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 1743217369 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 971079353 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 39316255 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 11053475 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 315918342 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups 168 # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups 4360508786 # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles 6080 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 557 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 18505861 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 554 # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads 3126877109 # The number of ROB reads
-system.cpu.rob.rob_writes 3611419620 # The number of ROB writes
-system.cpu.timesIdled 237370 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:BlockCycles 64472267 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 1425688721 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents 52544368 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 479786184 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 82632603 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 8428 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 5772028874 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 2456264739 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 2290118455 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 385614091 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 113949773 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 153477395 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 864429734 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups 19762 # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups 5772009112 # Number of integer rename lookups
+system.cpu.rename.RENAME:serializeStallCycles 19936 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 2550 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 360051799 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 2561 # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads 3418371032 # The number of ROB reads
+system.cpu.rob.rob_writes 4851844016 # The number of ROB writes
+system.cpu.timesIdled 625791 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 551 # Number of system calls
---------- End Simulation Statistics ----------
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing
+cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing
egid=100
env=
errout=cerr
All Rights Reserved
-M5 compiled Feb 8 2011 00:58:32
-M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip
-M5 started Feb 8 2011 00:58:34
+M5 compiled Feb 12 2011 02:22:23
+M5 revision 5e76f9de6972 7961 default qtip tip x86branchdetectstats.patch
+M5 started Feb 12 2011 02:22:27
M5 executing on burrito
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/o3-timing
+command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 114045138500 because target called exit()
+122 123 124 Exiting @ tick 108875474000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 187440 # Simulator instruction rate (inst/s)
-host_mem_usage 240848 # Number of bytes of host memory used
-host_seconds 1180.98 # Real time elapsed on the host
-host_tick_rate 96568147 # Simulator tick rate (ticks/s)
+host_inst_rate 92938 # Simulator instruction rate (inst/s)
+host_mem_usage 245208 # Number of bytes of host memory used
+host_seconds 2381.84 # Real time elapsed on the host
+host_tick_rate 45710653 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 221363017 # Number of instructions simulated
-sim_seconds 0.114045 # Number of seconds simulated
-sim_ticks 114045138500 # Number of ticks simulated
+sim_seconds 0.108875 # Number of seconds simulated
+sim_ticks 108875474000 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 15975516 # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 17934192 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 19725800 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 22620341 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect 3581786 # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 18022710 # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 18022710 # Number of BP lookups
+system.cpu.BPredUnit.condIncorrect 3050205 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 25317132 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 25317132 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 12326943 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 723634 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 2257656 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 220177428 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean 1.005385 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev 1.254706 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 193712128 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 1.142742 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 1.492040 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 88641889 40.26% 40.26% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1 86561337 39.31% 79.57% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2 21386723 9.71% 89.29% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3 12188145 5.54% 94.82% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4 6588488 2.99% 97.82% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5 2070275 0.94% 98.76% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6 1149159 0.52% 99.28% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7 867778 0.39% 99.67% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 723634 0.33% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 76077426 39.27% 39.27% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 72463860 37.41% 76.68% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 18818378 9.71% 86.40% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 12600057 6.50% 92.90% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 5960288 3.08% 95.98% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 2688234 1.39% 97.37% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 1804943 0.93% 98.30% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 1041286 0.54% 98.83% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 2257656 1.17% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 220177428 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 193712128 # Number of insts commited each cycle
system.cpu.commit.COM:count 221363017 # Number of instructions committed
system.cpu.commit.COM:fp_insts 2162459 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 77165306 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 3581794 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 3050238 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 221363017 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 48027716 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 180173936 # The number of squashed insts skipped by commit
system.cpu.committedInsts 221363017 # Number of Instructions Simulated
system.cpu.committedInsts_total 221363017 # Number of Instructions Simulated
-system.cpu.cpi 1.030390 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.030390 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 50422643 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 32842.809365 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34433.615819 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 50422045 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 19640000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.000012 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 598 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 244 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 12189500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.000007 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 354 # number of ReadReq MSHR misses
+system.cpu.cpi 0.983683 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.983683 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 50495037 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 33300.295858 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34031.250000 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 50494361 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 22511000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 676 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 292 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 13068000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 384 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 26406.061747 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35285.532995 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 20510418 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 140269000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.000259 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 5312 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 3736 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 55610000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000077 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 1576 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 26250.708416 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35437.100894 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 20508672 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 185277500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.000344 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 7058 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 5492 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 55494500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000076 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 1566 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 36752.571503 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 36411.811795 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 70938373 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 27057.360406 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 35129.274611 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 70932463 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 159909000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.000083 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 5910 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 3980 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 67799500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_accesses 71010767 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 26866.886475 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 35160.256410 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 71003033 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 207788500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.000109 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 7734 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 5784 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 68562500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000027 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 1930 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses 1950 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.336507 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 1378.331851 # Average occupied blocks per context
-system.cpu.dcache.overall_accesses 70938373 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 27057.360406 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 35129.274611 # average overall mshr miss latency
+system.cpu.dcache.occ_%::0 0.340706 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 1395.531138 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses 71010767 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 26866.886475 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 35160.256410 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 70932463 # number of overall hits
-system.cpu.dcache.overall_miss_latency 159909000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.000083 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 5910 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 3980 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 67799500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_hits 71003033 # number of overall hits
+system.cpu.dcache.overall_miss_latency 207788500 # number of overall miss cycles
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+system.cpu.dcache.overall_misses 7734 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 5784 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_rate 0.000027 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 1930 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses 1950 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 47 # number of replacements
-system.cpu.dcache.sampled_refs 1930 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 48 # number of replacements
+system.cpu.dcache.sampled_refs 1950 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 1378.331851 # Cycle average of tags in use
-system.cpu.dcache.total_refs 70932463 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 1395.531138 # Cycle average of tags in use
+system.cpu.dcache.total_refs 71003033 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 10 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 1914286 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts 286005423 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 48312658 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 169297181 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 7787199 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles 653303 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 18022710 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 18867666 # Number of cache lines fetched
-system.cpu.fetch.Cycles 179995924 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 191272 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 169328996 # Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles 11 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles 3686154 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.079016 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 18867666 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 15975516 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 0.742377 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 227964627 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.282286 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 1.366402 # Number of instructions fetched each cycle (Total)
+system.cpu.decode.DECODE:BlockedCycles 58788191 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 426377378 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 67892396 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 61042516 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 23949638 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:UnblockCycles 5989025 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 25317132 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 27858568 # Number of cache lines fetched
+system.cpu.fetch.Cycles 70494302 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 451015 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 267008364 # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles 3227425 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.116266 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 27858568 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 19725800 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.226210 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 217661766 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.006543 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.224025 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 54957212 24.11% 24.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 110607036 48.52% 72.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 34696842 15.22% 87.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 19348316 8.49% 96.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1875902 0.82% 97.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1062317 0.47% 97.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 939798 0.41% 98.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1341 0.00% 98.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 4475863 1.96% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 148998369 68.45% 68.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 3780164 1.74% 70.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 3170889 1.46% 71.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 4293321 1.97% 73.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 4655999 2.14% 75.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 4463846 2.05% 77.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 5161555 2.37% 80.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 3267808 1.50% 81.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 39869815 18.32% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 227964627 # Number of instructions fetched each cycle (Total)
-system.cpu.fp_regfile_reads 3211744 # number of floating regfile reads
-system.cpu.fp_regfile_writes 2048533 # number of floating regfile writes
-system.cpu.icache.ReadReq_accesses 18867666 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 25730.265551 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 22379.751901 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 18862168 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 141465000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000291 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 5498 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 500 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 111854000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000265 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 4998 # number of ReadReq MSHR misses
+system.cpu.fetch.rateDist::total 217661766 # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads 3513078 # number of floating regfile reads
+system.cpu.fp_regfile_writes 2177890 # number of floating regfile writes
+system.cpu.icache.ReadReq_accesses 27858568 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 25516.664059 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 22464.816190 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 27852177 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 163077000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000229 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 6391 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 1005 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 120995500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000193 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 5386 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 3774.698419 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 5171.217416 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 18867666 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 25730.265551 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 22379.751901 # average overall mshr miss latency
-system.cpu.icache.demand_hits 18862168 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 141465000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000291 # miss rate for demand accesses
-system.cpu.icache.demand_misses 5498 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 500 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 111854000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000265 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 4998 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses 27858568 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 25516.664059 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 22464.816190 # average overall mshr miss latency
+system.cpu.icache.demand_hits 27852177 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 163077000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000229 # miss rate for demand accesses
+system.cpu.icache.demand_misses 6391 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 1005 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 120995500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000193 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 5386 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.745890 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 1527.583314 # Average occupied blocks per context
-system.cpu.icache.overall_accesses 18867666 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 25730.265551 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 22379.751901 # average overall mshr miss latency
+system.cpu.icache.occ_%::0 0.783470 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 1604.546925 # Average occupied blocks per context
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+system.cpu.icache.overall_avg_miss_latency 25516.664059 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 22464.816190 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 18862168 # number of overall hits
-system.cpu.icache.overall_miss_latency 141465000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000291 # miss rate for overall accesses
-system.cpu.icache.overall_misses 5498 # number of overall misses
-system.cpu.icache.overall_mshr_hits 500 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 111854000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000265 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 4998 # number of overall MSHR misses
+system.cpu.icache.overall_hits 27852177 # number of overall hits
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+system.cpu.icache.overall_misses 6391 # number of overall misses
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+system.cpu.icache.overall_mshr_miss_latency 120995500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000193 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 5386 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 3094 # number of replacements
-system.cpu.icache.sampled_refs 4997 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 3428 # number of replacements
+system.cpu.icache.sampled_refs 5386 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1527.583314 # Cycle average of tags in use
-system.cpu.icache.total_refs 18862168 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 1604.546925 # Cycle average of tags in use
+system.cpu.icache.total_refs 27852177 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 125651 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 13177188 # Number of branches executed
+system.cpu.idleCycles 89183 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 15799905 # Number of branches executed
system.cpu.iew.EXEC:nop 0 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.062789 # Inst execution rate
-system.cpu.iew.EXEC:refs 86183722 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 21962366 # Number of stores executed
+system.cpu.iew.EXEC:rate 1.276995 # Inst execution rate
+system.cpu.iew.EXEC:refs 89573185 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 22888685 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 296340219 # num instructions consuming a value
-system.cpu.iew.WB:count 239588905 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.644617 # average fanout of values written-back
+system.cpu.iew.WB:consumers 372933305 # num instructions consuming a value
+system.cpu.iew.WB:count 276026292 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.598611 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 191026075 # num instructions producing a value
-system.cpu.iew.WB:rate 1.050413 # insts written-back per cycle
-system.cpu.iew.WB:sent 240106417 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 3659082 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 1291 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 69776556 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 1273 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 2389686 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 24137923 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 269390730 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 64221356 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 3582148 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 242411882 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 27 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers 223241922 # num instructions producing a value
+system.cpu.iew.WB:rate 1.267624 # insts written-back per cycle
+system.cpu.iew.WB:sent 277033647 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 3251135 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 619969 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 106923422 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 1424 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 171683 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 37463806 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 401512728 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 66684500 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 3440679 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 278066855 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 560615 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 7787199 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 324 # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents 30447 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 23949638 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 623802 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 13515418 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 128079 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.forwLoads 15985064 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 21414 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 128891 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 44661 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 13126966 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 3622207 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 128891 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 152659 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 3506423 # Number of branches that were predicted taken incorrectly
-system.cpu.int_regfile_reads 488710459 # number of integer regfile reads
-system.cpu.int_regfile_writes 250225793 # number of integer regfile writes
-system.cpu.ipc 0.970506 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.970506 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0::No_OpClass 1179793 0.48% 0.48% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu 155739742 63.31% 63.79% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 63.79% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 63.79% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd 1520188 0.62% 64.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 64.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 64.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 64.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 64.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 64.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 64.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 64.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 64.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 64.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 64.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 64.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 64.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 64.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 64.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 64.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 64.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 64.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 64.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 64.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 64.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 64.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 64.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 64.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 64.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 64.41% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead 65456200 26.61% 91.02% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite 22098107 8.98% 100.00% # Type of FU issued
+system.cpu.iew.lsq.thread.0.memOrderViolation 187512 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 45117 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 50273832 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 16948090 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 187512 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 737658 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 2513477 # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads 514946932 # number of integer regfile reads
+system.cpu.int_regfile_writes 284476955 # number of integer regfile writes
+system.cpu.ipc 1.016588 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.016588 # IPC: Total IPC of All Threads
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+system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.61% # Type of FU issued
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+system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.61% # Type of FU issued
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+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 67.61% # Type of FU issued
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+system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 67.61% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total 245994030 # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt 166267 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.000676 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total 281507534 # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt 2779468 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.009874 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu 4 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.00% # attempts to use FU when none available
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-system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.00% # attempts to use FU when none available
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-system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead 131346 79.00% 79.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite 34917 21.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu 58461 2.10% 2.10% # attempts to use FU when none available
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+system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.10% # attempts to use FU when none available
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+system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.10% # attempts to use FU when none available
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+system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 2.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 2.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 2.10% # attempts to use FU when none available
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+system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 2.10% # attempts to use FU when none available
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+system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 2.10% # attempts to use FU when none available
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+system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 2.10% # attempts to use FU when none available
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system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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-system.cpu.iq.ISSUE:issued_per_cycle::mean 1.079089 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev 0.987640 # Number of insts issued each cycle
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+system.cpu.iq.ISSUE:issued_per_cycle::mean 1.293326 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.357747 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0 72171112 31.66% 31.66% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1 90119003 39.53% 71.19% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2 46322685 20.32% 91.51% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3 15038489 6.60% 98.11% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4 3583873 1.57% 99.68% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5 613391 0.27% 99.95% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6 102303 0.04% 99.99% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7 12243 0.01% 100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8 1528 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0 75328501 34.61% 34.61% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1 67045740 30.80% 65.41% # Number of insts issued each cycle
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+system.cpu.iq.ISSUE:issued_per_cycle::3 20059185 9.22% 91.94% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4 11722195 5.39% 97.32% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5 3737927 1.72% 99.04% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6 1378220 0.63% 99.67% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7 597426 0.27% 99.95% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8 111563 0.05% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total 227964627 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate 1.078494 # Inst issue rate
-system.cpu.iq.fp_alu_accesses 2547074 # Number of floating point alu accesses
-system.cpu.iq.fp_inst_queue_reads 5090153 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_wakeup_accesses 2386799 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_writes 3193028 # Number of floating instruction queue writes
-system.cpu.iq.int_alu_accesses 242433430 # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads 715029059 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses 237202106 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes 313965679 # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded 269389457 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 245994030 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 1273 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 47650161 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 258 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 27 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 91534276 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadExReq_accesses 1576 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34382.484076 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31064.649682 # average ReadExReq mshr miss latency
+system.cpu.iq.ISSUE:issued_per_cycle::total 217661766 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate 1.292796 # Inst issue rate
+system.cpu.iq.fp_alu_accesses 2630821 # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads 5219937 # Number of floating instruction queue reads
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+system.cpu.iq.fp_inst_queue_writes 5714467 # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses 280460790 # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads 778290063 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses 273499649 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes 575780653 # Number of integer instruction queue writes
+system.cpu.iq.iqInstsAdded 401511304 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 281507534 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 1424 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 179800569 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 53698 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 178 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 375388973 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadExReq_accesses 1566 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34512.500000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31347.756410 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 6 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency 53980500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 0.996193 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 1570 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 48771500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.996193 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 1570 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 5352 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34258.559622 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31035.566706 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 1964 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 116068000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.633034 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 3388 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 105148500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.633034 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 3388 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_miss_latency 53839500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 0.996169 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 1560 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 48902500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.996169 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 1560 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 5770 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34287.021858 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31043.032787 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 2110 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 125490500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.634315 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 3660 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 113617500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.634315 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 3660 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 10 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 10 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.579180 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.575873 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 6928 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34297.801533 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31044.776119 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 1970 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 170048500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.715647 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 4958 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 7336 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34354.406130 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31134.099617 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 2116 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 179330000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.711559 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 5220 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 153920000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.715647 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 4958 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 162520000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.711559 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 5220 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.067776 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::0 0.074027 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.000031 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 2220.891460 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 1.016755 # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses 6928 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34297.801533 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31044.776119 # average overall mshr miss latency
+system.cpu.l2cache.occ_blocks::0 2425.713909 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 1.014918 # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses 7336 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34354.406130 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31134.099617 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 1970 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 170048500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.715647 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 4958 # number of overall misses
+system.cpu.l2cache.overall_hits 2116 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 179330000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.711559 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 5220 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 153920000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.715647 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 4958 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 162520000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.711559 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 5220 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 3391 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 3664 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 2221.908214 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1964 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 2426.728827 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 2110 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.memDep0.conflictingLoads 28553702 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 6206376 # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads 69776556 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 24137923 # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads 125230087 # number of misc regfile reads
+system.cpu.memDep0.conflictingLoads 95035235 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 32152607 # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads 106923422 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 37463806 # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads 144601816 # number of misc regfile reads
system.cpu.misc_regfile_writes 844 # number of misc regfile writes
-system.cpu.numCycles 228090278 # number of cpu cycles simulated
+system.cpu.numCycles 217750949 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles 31917 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:BlockCycles 18951054 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 234363409 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 638720 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 52054674 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 682190 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 732163494 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 280433210 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 305502440 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 166205742 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 7787199 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 1869216 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 71139031 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups 7184355 # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups 724979139 # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles 15879 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 1273 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 3670415 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 1276 # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads 488844527 # The number of ROB reads
-system.cpu.rob.rob_writes 546568715 # The number of ROB writes
-system.cpu.timesIdled 2341 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:IQFullEvents 22087788 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 75841753 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 16619805 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 9 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 1071149424 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 415976206 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 437655168 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 58179410 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 23949638 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 40717504 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 203291759 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups 11132052 # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups 1060017372 # Number of integer rename lookups
+system.cpu.rename.RENAME:serializeStallCycles 22407 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 1440 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 84366850 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 1310 # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads 592991425 # The number of ROB reads
+system.cpu.rob.rob_writes 827053987 # The number of ROB writes
+system.cpu.timesIdled 1919 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 400 # Number of system calls
---------- End Simulation Statistics ----------
All Rights Reserved
-M5 compiled Feb 8 2011 00:58:32
-M5 revision 705a4d351a43 7939 default qtip resforflagsstats.patch tip
-M5 started Feb 8 2011 00:58:34
+M5 compiled Feb 12 2011 02:22:23
+M5 revision 5e76f9de6972 7961 default qtip tip x86branchdetectstats.patch
+M5 started Feb 12 2011 02:22:27
M5 executing on burrito
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/o3-timing
+command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 13637500 because target called exit()
+Exiting @ tick 11421500 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 59245 # Simulator instruction rate (inst/s)
-host_mem_usage 228168 # Number of bytes of host memory used
-host_seconds 0.17 # Real time elapsed on the host
-host_tick_rate 82238527 # Simulator tick rate (ticks/s)
+host_inst_rate 47598 # Simulator instruction rate (inst/s)
+host_mem_usage 231896 # Number of bytes of host memory used
+host_seconds 0.21 # Real time elapsed on the host
+host_tick_rate 55349277 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 9809 # Number of instructions simulated
-sim_seconds 0.000014 # Number of seconds simulated
-sim_ticks 13637500 # Number of ticks simulated
+sim_seconds 0.000011 # Number of seconds simulated
+sim_ticks 11421500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 715 # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 1829 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 944 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 2550 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect 455 # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 1876 # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 1876 # Number of BP lookups
+system.cpu.BPredUnit.condIncorrect 485 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 2777 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 2777 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 1214 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 22 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 139 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 15018 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean 0.653150 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev 1.090994 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 11906 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 0.823870 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 1.588166 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 9552 63.60% 63.60% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1 2996 19.95% 83.55% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2 1196 7.96% 91.52% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3 909 6.05% 97.57% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4 244 1.62% 99.19% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5 60 0.40% 99.59% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6 31 0.21% 99.80% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7 8 0.05% 99.85% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 22 0.15% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 8274 69.49% 69.49% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 1230 10.33% 79.83% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 588 4.94% 84.76% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 963 8.09% 92.85% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 395 3.32% 96.17% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 136 1.14% 97.31% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 125 1.05% 98.36% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 56 0.47% 98.83% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 139 1.17% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 15018 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 11906 # Number of insts commited each cycle
system.cpu.commit.COM:count 9809 # Number of instructions committed
system.cpu.commit.COM:fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 1990 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 455 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 485 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 9809 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 3810 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 9374 # The number of squashed insts skipped by commit
system.cpu.committedInsts 9809 # Number of Instructions Simulated
system.cpu.committedInsts_total 9809 # Number of Instructions Simulated
-system.cpu.cpi 2.780712 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 2.780712 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 1299 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 34989.361702 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34992.307692 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 1205 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 3289000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.072363 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 94 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 29 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 2274500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.050038 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 65 # number of ReadReq MSHR misses
+system.cpu.cpi 2.328882 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 2.328882 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 1541 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 34473.684211 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35119.402985 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 1427 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 3930000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.073978 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 114 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 47 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 2353000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.043478 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 67 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 33138.977636 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35814.102564 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 34089.456869 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36012.987013 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 621 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 10372500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 10670000 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.335118 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 313 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 235 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 2793500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.083512 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 78 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_hits 236 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 2773000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.082441 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 77 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 12.859155 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 14.321678 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 2233 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 33566.339066 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 35440.559441 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 1826 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 13661500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.182266 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 407 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 264 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 5068000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.064039 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 143 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 2475 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 34192.037471 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 35597.222222 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 2048 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 14600000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.172525 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 427 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 283 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 5126000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.058182 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 144 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.021266 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 87.104239 # Average occupied blocks per context
-system.cpu.dcache.overall_accesses 2233 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 33566.339066 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 35440.559441 # average overall mshr miss latency
+system.cpu.dcache.occ_%::0 0.020970 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 85.892970 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses 2475 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 34192.037471 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 35597.222222 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 1826 # number of overall hits
-system.cpu.dcache.overall_miss_latency 13661500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.182266 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 407 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 264 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 5068000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.064039 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 143 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 2048 # number of overall hits
+system.cpu.dcache.overall_miss_latency 14600000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.172525 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 427 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 283 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 5126000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.058182 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 144 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks.
+system.cpu.dcache.sampled_refs 143 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 87.104239 # Cycle average of tags in use
-system.cpu.dcache.total_refs 1826 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 85.892970 # Cycle average of tags in use
+system.cpu.dcache.total_refs 2048 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 420 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts 15296 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 6181 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 8360 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 701 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles 57 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 1876 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 1264 # Number of cache lines fetched
-system.cpu.fetch.Cycles 9026 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 121 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 8825 # Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles 464 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.068778 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 1264 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 715 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 0.323545 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 15719 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.009352 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 1.179835 # Number of instructions fetched each cycle (Total)
+system.cpu.decode.DECODE:BlockedCycles 1367 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 22275 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 7155 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 3308 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 1504 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:UnblockCycles 76 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 2777 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 1732 # Number of cache lines fetched
+system.cpu.fetch.Cycles 3623 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 245 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 12976 # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles 508 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.121564 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 1732 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 944 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 0.568027 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 13410 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.734526 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.109133 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 7007 44.58% 44.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 4504 28.65% 73.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1838 11.69% 84.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2072 13.18% 98.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 57 0.36% 98.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 222 1.41% 99.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 6 0.04% 99.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 8 0.05% 99.97% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 5 0.03% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 9877 73.65% 73.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 162 1.21% 74.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 123 0.92% 75.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 227 1.69% 77.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 192 1.43% 78.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 174 1.30% 80.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 266 1.98% 82.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 175 1.30% 83.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 2214 16.51% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 15719 # Number of instructions fetched each cycle (Total)
-system.cpu.fp_regfile_reads 2 # number of floating regfile reads
-system.cpu.icache.ReadReq_accesses 1264 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 37405.594406 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35046.332046 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 978 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 10698000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.226266 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 286 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 27 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 9077000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.204905 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 259 # number of ReadReq MSHR misses
+system.cpu.fetch.rateDist::total 13410 # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads 4 # number of floating regfile reads
+system.cpu.icache.ReadReq_accesses 1732 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 36454.794521 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 35105.084746 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 1367 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 13306000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.210739 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 365 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 70 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 10356000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.170323 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 295 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 3.776062 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 4.633898 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 1264 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 37405.594406 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35046.332046 # average overall mshr miss latency
-system.cpu.icache.demand_hits 978 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 10698000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.226266 # miss rate for demand accesses
-system.cpu.icache.demand_misses 286 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 27 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 9077000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.204905 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 259 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses 1732 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 36454.794521 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 35105.084746 # average overall mshr miss latency
+system.cpu.icache.demand_hits 1367 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 13306000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.210739 # miss rate for demand accesses
+system.cpu.icache.demand_misses 365 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 70 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 10356000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.170323 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 295 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.062320 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 127.631724 # Average occupied blocks per context
-system.cpu.icache.overall_accesses 1264 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 37405.594406 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35046.332046 # average overall mshr miss latency
+system.cpu.icache.occ_%::0 0.070726 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 144.846093 # Average occupied blocks per context
+system.cpu.icache.overall_accesses 1732 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 36454.794521 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 35105.084746 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 978 # number of overall hits
-system.cpu.icache.overall_miss_latency 10698000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.226266 # miss rate for overall accesses
-system.cpu.icache.overall_misses 286 # number of overall misses
-system.cpu.icache.overall_mshr_hits 27 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 9077000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.204905 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 259 # number of overall MSHR misses
+system.cpu.icache.overall_hits 1367 # number of overall hits
+system.cpu.icache.overall_miss_latency 13306000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.210739 # miss rate for overall accesses
+system.cpu.icache.overall_misses 365 # number of overall misses
+system.cpu.icache.overall_mshr_hits 70 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 10356000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.170323 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 295 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.sampled_refs 259 # Sample count of references to valid blocks.
+system.cpu.icache.sampled_refs 295 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 127.631724 # Cycle average of tags in use
-system.cpu.icache.total_refs 978 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 144.846093 # Cycle average of tags in use
+system.cpu.icache.total_refs 1367 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 11557 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 1339 # Number of branches executed
+system.cpu.idleCycles 9434 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 1551 # Number of branches executed
system.cpu.iew.EXEC:nop 0 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.445373 # Inst execution rate
-system.cpu.iew.EXEC:refs 2437 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 1088 # Number of stores executed
+system.cpu.iew.EXEC:rate 0.676151 # Inst execution rate
+system.cpu.iew.EXEC:refs 2971 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 1306 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 9192 # num instructions consuming a value
-system.cpu.iew.WB:count 11991 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.803198 # average fanout of values written-back
+system.cpu.iew.WB:consumers 14704 # num instructions consuming a value
+system.cpu.iew.WB:count 15138 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.679747 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 7383 # num instructions producing a value
-system.cpu.iew.WB:rate 0.439617 # insts written-back per cycle
-system.cpu.iew.WB:sent 12024 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 474 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 40 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 1510 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 16 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 424 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 1230 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 13620 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 1349 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 556 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 12148 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers 9995 # num instructions producing a value
+system.cpu.iew.WB:rate 0.662669 # insts written-back per cycle
+system.cpu.iew.WB:sent 15263 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 565 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 187 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 2105 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 207 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 1639 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 19184 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 1665 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 710 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 15446 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 701 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking
+system.cpu.iew.iewSquashCycles 1504 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 20 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 23 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.forwLoads 68 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 10 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 454 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 296 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 385 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 89 # Number of branches that were predicted taken incorrectly
-system.cpu.int_regfile_reads 19557 # number of integer regfile reads
-system.cpu.int_regfile_writes 11326 # number of integer regfile writes
-system.cpu.ipc 0.359620 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.359620 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued
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-system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 79.85% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 79.85% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 79.85% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 79.85% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 79.85% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 79.85% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 79.85% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 79.85% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 79.85% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 79.85% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 79.85% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 79.85% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 79.85% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 79.85% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 79.85% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 79.85% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 79.85% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 79.85% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 79.85% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 79.85% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 79.85% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 79.85% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 79.85% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 79.85% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 0 0.00% 79.85% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 79.85% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 79.85% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 79.85% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead 1414 11.13% 90.98% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite 1146 9.02% 100.00% # Type of FU issued
+system.cpu.iew.lsq.thread.0.memOrderViolation 31 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 1049 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 705 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 31 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 496 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads 23051 # number of integer regfile reads
+system.cpu.int_regfile_writes 14062 # number of integer regfile writes
+system.cpu.ipc 0.429391 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.429391 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued
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+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 80.29% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total 12704 # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt 4 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.000315 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total 16156 # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt 142 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.008789 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.00% # attempts to use FU when none available
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-system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead 4 100.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite 0 0.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu 97 68.31% 68.31% # attempts to use FU when none available
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+system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 68.31% # attempts to use FU when none available
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+system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 68.31% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 68.31% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 68.31% # attempts to use FU when none available
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+system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 68.31% # attempts to use FU when none available
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+system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 68.31% # attempts to use FU when none available
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+system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 68.31% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 68.31% # attempts to use FU when none available
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+system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 68.31% # attempts to use FU when none available
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system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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-system.cpu.iq.ISSUE:issued_per_cycle::mean 0.808194 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev 0.980491 # Number of insts issued each cycle
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+system.cpu.iq.ISSUE:issued_per_cycle::mean 1.204773 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.912582 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0 7896 50.23% 50.23% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1 4146 26.38% 76.61% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2 2688 17.10% 93.71% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3 806 5.13% 98.84% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4 156 0.99% 99.83% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5 22 0.14% 99.97% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6 5 0.03% 100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0 8282 61.76% 61.76% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1 1307 9.75% 71.51% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2 986 7.35% 78.86% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3 745 5.56% 84.41% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4 787 5.87% 90.28% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5 588 4.38% 94.67% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6 498 3.71% 98.38% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7 170 1.27% 99.65% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8 47 0.35% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::max_value 6 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total 15719 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate 0.465757 # Inst issue rate
-system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
-system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes
-system.cpu.iq.int_alu_accesses 12701 # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads 41124 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses 11989 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes 16903 # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded 13604 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 12704 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 16 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 3282 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 3903 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadExReq_accesses 78 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34512.820513 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31358.974359 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 2692000 # number of ReadExReq miss cycles
+system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::total 13410 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate 0.707232 # Inst issue rate
+system.cpu.iq.fp_alu_accesses 5 # Number of floating point alu accesses
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+system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses 16289 # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads 45908 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses 15134 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes 27963 # Number of integer instruction queue writes
+system.cpu.iq.iqInstsAdded 19154 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 16156 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 8758 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 11067 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadExReq_accesses 77 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34616.883117 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31389.610390 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 2665500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 78 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 2446000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_misses 77 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 2417000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 78 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 324 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34181.677019 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 30998.447205 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_misses 77 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 362 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34245.833333 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31040.277778 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 11006500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.993827 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 322 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 9981500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.993827 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 322 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_miss_latency 12328500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.994475 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 360 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 11174500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994475 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 360 # number of ReadReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.006231 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.005571 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 402 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34246.250000 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31068.750000 # average overall mshr miss latency
+system.cpu.l2cache.demand_accesses 439 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34311.212815 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31101.830664 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 13698500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.995025 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 400 # number of demand (read+write) misses
+system.cpu.l2cache.demand_miss_latency 14994000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.995444 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 437 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 12427500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.995025 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 400 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 13591500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.995444 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 437 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.004917 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 161.123348 # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses 402 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34246.250000 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31068.750000 # average overall mshr miss latency
+system.cpu.l2cache.occ_%::0 0.005436 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 178.138745 # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses 439 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34311.212815 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31101.830664 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 2 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 13698500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.995025 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 400 # number of overall misses
+system.cpu.l2cache.overall_miss_latency 14994000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.995444 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 437 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 12427500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.995025 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 400 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 13591500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.995444 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 437 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 321 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 161.123348 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 178.138745 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads 1510 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1230 # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads 5444 # number of misc regfile reads
-system.cpu.numCycles 27276 # number of cpu cycles simulated
+system.cpu.memDep0.conflictingLoads 24 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads 2105 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1639 # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads 6857 # number of misc regfile reads
+system.cpu.numCycles 22844 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles 87 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:BlockCycles 565 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 9368 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 6 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 6548 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 15 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 31415 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 14729 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 13866 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 8021 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 701 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 105 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 4498 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:IQFullEvents 51 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 7399 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 247 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 3 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 44700 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 21187 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 19905 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 3124 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 1504 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 378 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 10537 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 16 # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups 31399 # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles 257 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 19 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 159 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 16 # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads 28615 # The number of ROB reads
-system.cpu.rob.rob_writes 27943 # The number of ROB writes
-system.cpu.timesIdled 206 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:int_rename_lookups 44684 # Number of integer rename lookups
+system.cpu.rename.RENAME:serializeStallCycles 440 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 32 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 1476 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 31 # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads 30950 # The number of ROB reads
+system.cpu.rob.rob_writes 39896 # The number of ROB writes
+system.cpu.timesIdled 184 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
---------- End Simulation Statistics ----------
projects / gem5.git / commitdiff