Fix up some ISA related stuff.

arch/alpha/isa/decoder.isa:
    Marked a few more instructions as unverifiable.
arch/alpha/isa/mem.isa:
    Warn instead of panic, otherwise this can cause the simulation to fail even if the instruction is never committed.

--HG--
extra : convert_revision : 12befc6fedd1a6883d0517e649ad01b91fb561ae

diff --git a/arch/alpha/isa/decoder.isa b/arch/alpha/isa/decoder.isa
index b3744a43d06472f5077958f995b4d4caef08795a..71b9131aadfc14f95fea45ac3e639f41ac6ada40 100644 (file)
--- a/arch/alpha/isa/decoder.isa
+++ b/arch/alpha/isa/decoder.isa
@@ -694,7 +694,7 @@ decode OPCODE default Unknown::unknown() {
             }}, IsNonSpeculative);
             0x83: callsys({{
                 xc->syscall();
-            }}, IsNonSpeculative);
+            }}, IsNonSpeculative, IsSerializeAfter);
             // Read uniq reg into ABI return value register (r0)
             0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess);
             // Write uniq reg with value from ABI arg register (r16)
@@ -768,10 +768,10 @@ decode OPCODE default Unknown::unknown() {
             }}, IsNonSpeculative, IsQuiesce);
             0x03: quiesceCycles({{
                 AlphaPseudo::quiesceCycles(xc->xcBase(), R16);
-            }}, IsNonSpeculative, IsQuiesce);
+            }}, IsNonSpeculative, IsQuiesce, IsUnverifiable);
             0x04: quiesceTime({{
                 R0 = AlphaPseudo::quiesceTime(xc->xcBase());
-            }}, IsNonSpeculative);
+            }}, IsNonSpeculative, IsUnverifiable);
             0x10: ivlb({{
                 AlphaPseudo::ivlb(xc->xcBase());
             }}, No_OpClass, IsNonSpeculative);

diff --git a/arch/alpha/isa/mem.isa b/arch/alpha/isa/mem.isa
index 3c8b4f7554f80639482be62a35a4db4be7ff282f..5d29c18bcfcf17875e7f64f49d2b5747e41c4cc8 100644 (file)
--- a/arch/alpha/isa/mem.isa
+++ b/arch/alpha/isa/mem.isa
@@ -500,7 +500,7 @@ def template MiscInitiateAcc {{
     Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
                                       Trace::InstRecord *traceData) const
     {
-        panic("Misc instruction does not support split access method!");
+        warn("Misc instruction does not support split access method!");
         return NoFault;
     }
 }};
@@ -511,7 +511,7 @@ def template MiscCompleteAcc {{
                                       %(CPU_exec_context)s *xc,
                                       Trace::InstRecord *traceData) const
     {
-        panic("Misc instruction does not support split access method!");
+        warn("Misc instruction does not support split access method!");
 
         return NoFault;
     }