Remove -icells

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 3525e4de90cc8dfd83ed14763cd9003a964886d8..d4874af452f39e2e411707479317a331a4c8de81 100644 (file)
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -230,9 +230,9 @@ struct SynthXilinxPass : public ScriptPass
        {
                if (check_label("begin")) {
                        if (vpr)
-                               run("read_verilog -lib -icells -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
+                               run("read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
                        else
-                               run("read_verilog -lib -icells +/xilinx/cells_sim.v");
+                               run("read_verilog -lib +/xilinx/cells_sim.v");
 
                        run("read_verilog -lib +/xilinx/cells_xtra.v");