/* Tiled textures are unmappable. Always put them in VRAM. */
if ((res->b.b.target != PIPE_BUFFER && !rtex->surface.is_linear) ||
- res->b.b.flags & R600_RESOURCE_FLAG_UNMAPPABLE) {
+ res->b.b.flags & SI_RESOURCE_FLAG_UNMAPPABLE) {
res->domains = RADEON_DOMAIN_VRAM;
res->flags |= RADEON_FLAG_NO_CPU_ACCESS |
RADEON_FLAG_GTT_WC;
if (sscreen->debug_flags & DBG(NO_WC))
res->flags &= ~RADEON_FLAG_GTT_WC;
- if (res->b.b.flags & R600_RESOURCE_FLAG_READ_ONLY)
+ if (res->b.b.flags & SI_RESOURCE_FLAG_READ_ONLY)
res->flags |= RADEON_FLAG_READ_ONLY;
- if (res->b.b.flags & R600_RESOURCE_FLAG_32BIT)
+ if (res->b.b.flags & SI_RESOURCE_FLAG_32BIT)
res->flags |= RADEON_FLAG_32BIT;
/* Set expected VRAM and GART usage for the buffer. */
struct r600_resource *staging = NULL;
u_upload_alloc(ctx->stream_uploader, 0,
- box->width + (box->x % R600_MAP_BUFFER_ALIGNMENT),
+ box->width + (box->x % SI_MAP_BUFFER_ALIGNMENT),
sctx->screen->info.tcc_cache_line_size,
&offset, (struct pipe_resource**)&staging,
(void**)&data);
if (staging) {
- data += box->x % R600_MAP_BUFFER_ALIGNMENT;
+ data += box->x % SI_MAP_BUFFER_ALIGNMENT;
return si_buffer_get_transfer(ctx, resource, usage, box,
ptransfer, data, staging, offset);
} else if (rbuffer->flags & RADEON_FLAG_SPARSE) {
assert(!(usage & TC_TRANSFER_MAP_THREADED_UNSYNC));
staging = (struct r600_resource*) pipe_buffer_create(
ctx->screen, 0, PIPE_USAGE_STAGING,
- box->width + (box->x % R600_MAP_BUFFER_ALIGNMENT));
+ box->width + (box->x % SI_MAP_BUFFER_ALIGNMENT));
if (staging) {
/* Copy the VRAM buffer to the staging buffer. */
sctx->b.dma_copy(ctx, &staging->b.b, 0,
- box->x % R600_MAP_BUFFER_ALIGNMENT,
+ box->x % SI_MAP_BUFFER_ALIGNMENT,
0, 0, resource, 0, box);
data = si_buffer_map_sync_with_rings(sctx, staging,
r600_resource_reference(&staging, NULL);
return NULL;
}
- data += box->x % R600_MAP_BUFFER_ALIGNMENT;
+ data += box->x % SI_MAP_BUFFER_ALIGNMENT;
return si_buffer_get_transfer(ctx, resource, usage, box,
ptransfer, data, staging, 0);
dst = transfer->resource;
src = &rtransfer->staging->b.b;
- soffset = rtransfer->offset + box->x % R600_MAP_BUFFER_ALIGNMENT;
+ soffset = rtransfer->offset + box->x % SI_MAP_BUFFER_ALIGNMENT;
u_box_1d(soffset, box->width, &dma_box);
struct r600_resource *rbuffer = si_alloc_buffer_struct(screen, templ);
if (templ->flags & PIPE_RESOURCE_FLAG_SPARSE)
- rbuffer->b.b.flags |= R600_RESOURCE_FLAG_UNMAPPABLE;
+ rbuffer->b.b.flags |= SI_RESOURCE_FLAG_UNMAPPABLE;
si_init_resource_fields(sscreen, rbuffer, templ->width0, alignment);
struct u_log_context;
struct si_screen;
struct si_context;
-
-#define R600_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
-#define R600_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
-#define R600_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
-#define R600_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
-#define R600_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
-#define R600_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
-#define R600_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
-
-/* Debug flags. */
-enum {
- /* Shader logging options: */
- DBG_VS = PIPE_SHADER_VERTEX,
- DBG_PS = PIPE_SHADER_FRAGMENT,
- DBG_GS = PIPE_SHADER_GEOMETRY,
- DBG_TCS = PIPE_SHADER_TESS_CTRL,
- DBG_TES = PIPE_SHADER_TESS_EVAL,
- DBG_CS = PIPE_SHADER_COMPUTE,
- DBG_NO_IR,
- DBG_NO_TGSI,
- DBG_NO_ASM,
- DBG_PREOPT_IR,
-
- /* Shader compiler options the shader cache should be aware of: */
- DBG_FS_CORRECT_DERIVS_AFTER_KILL,
- DBG_UNSAFE_MATH,
- DBG_SI_SCHED,
-
- /* Shader compiler options (with no effect on the shader cache): */
- DBG_CHECK_IR,
- DBG_NIR,
- DBG_MONOLITHIC_SHADERS,
- DBG_NO_OPT_VARIANT,
-
- /* Information logging options: */
- DBG_INFO,
- DBG_TEX,
- DBG_COMPUTE,
- DBG_VM,
-
- /* Driver options: */
- DBG_FORCE_DMA,
- DBG_NO_ASYNC_DMA,
- DBG_NO_WC,
- DBG_CHECK_VM,
- DBG_RESERVE_VMID,
-
- /* 3D engine options: */
- DBG_SWITCH_ON_EOP,
- DBG_NO_OUT_OF_ORDER,
- DBG_NO_DPBB,
- DBG_NO_DFSM,
- DBG_DPBB,
- DBG_DFSM,
- DBG_NO_HYPERZ,
- DBG_NO_RB_PLUS,
- DBG_NO_2D_TILING,
- DBG_NO_TILING,
- DBG_NO_DCC,
- DBG_NO_DCC_CLEAR,
- DBG_NO_DCC_FB,
- DBG_NO_DCC_MSAA,
- DBG_DCC_MSAA,
- DBG_NO_FMASK,
-
- /* Tests: */
- DBG_TEST_DMA,
- DBG_TEST_VMFAULT_CP,
- DBG_TEST_VMFAULT_SDMA,
- DBG_TEST_VMFAULT_SHADER,
-};
-
-#define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
-#define DBG(name) (1ull << DBG_##name)
-
-#define R600_MAP_BUFFER_ALIGNMENT 64
-
-#define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
-
struct si_perfcounters;
struct tgsi_shader_info;
struct si_qbo_state;
}
if (sscreen->info.chip_class >= VI &&
- (ptex->flags & R600_RESOURCE_FLAG_DISABLE_DCC ||
+ (ptex->flags & SI_RESOURCE_FLAG_DISABLE_DCC ||
ptex->format == PIPE_FORMAT_R9G9B9E5_FLOAT ||
/* DCC MSAA array textures are disallowed due to incomplete clear impl. */
(ptex->nr_samples >= 2 &&
flags |= RADEON_SURF_SHAREABLE;
if (is_imported)
flags |= RADEON_SURF_IMPORTED | RADEON_SURF_SHAREABLE;
- if (!(ptex->flags & R600_RESOURCE_FLAG_FORCE_TILING))
+ if (!(ptex->flags & SI_RESOURCE_FLAG_FORCE_TILING))
flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
r = sscreen->ws->surface_init(sscreen->ws, ptex, flags, bpe,
rtex->can_sample_s = !rtex->surface.u.legacy.stencil_adjusted;
}
- if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER |
- R600_RESOURCE_FLAG_FLUSHED_DEPTH))) {
+ if (!(base->flags & (SI_RESOURCE_FLAG_TRANSFER |
+ SI_RESOURCE_FLAG_FLUSHED_DEPTH))) {
rtex->db_compatible = true;
if (!(sscreen->debug_flags & DBG(NO_HYPERZ)))
const struct pipe_resource *templ)
{
const struct util_format_description *desc = util_format_description(templ->format);
- bool force_tiling = templ->flags & R600_RESOURCE_FLAG_FORCE_TILING;
+ bool force_tiling = templ->flags & SI_RESOURCE_FLAG_FORCE_TILING;
bool is_depth_stencil = util_format_is_depth_or_stencil(templ->format) &&
- !(templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH);
+ !(templ->flags & SI_RESOURCE_FLAG_FLUSHED_DEPTH);
/* MSAA resources must be 2D tiled. */
if (templ->nr_samples > 1)
return RADEON_SURF_MODE_2D;
/* Transfer resources should be linear. */
- if (templ->flags & R600_RESOURCE_FLAG_TRANSFER)
+ if (templ->flags & SI_RESOURCE_FLAG_TRANSFER)
return RADEON_SURF_MODE_LINEAR_ALIGNED;
/* Avoid Z/S decompress blits by forcing TC-compatible HTILE on VI,
{
struct si_screen *sscreen = (struct si_screen*)screen;
struct radeon_surf surface = {0};
- bool is_flushed_depth = templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH;
+ bool is_flushed_depth = templ->flags & SI_RESOURCE_FLAG_FLUSHED_DEPTH;
bool tc_compatible_htile =
sscreen->info.chip_class >= VI &&
(templ->flags & PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY) &&
resource.nr_samples = texture->nr_samples;
resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
- resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH;
+ resource.flags = texture->flags | SI_RESOURCE_FLAG_FLUSHED_DEPTH;
if (staging)
- resource.flags |= R600_RESOURCE_FLAG_TRANSFER;
+ resource.flags |= SI_RESOURCE_FLAG_TRANSFER;
*flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource);
if (*flushed_depth_texture == NULL) {
res->height0 = box->height;
res->depth0 = 1;
res->array_size = 1;
- res->usage = flags & R600_RESOURCE_FLAG_TRANSFER ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
+ res->usage = flags & SI_RESOURCE_FLAG_TRANSFER ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
res->flags = flags;
/* We must set the correct texture target and dimensions for a 3D box. */
char *map;
bool use_staging_texture = false;
- assert(!(texture->flags & R600_RESOURCE_FLAG_TRANSFER));
+ assert(!(texture->flags & SI_RESOURCE_FLAG_TRANSFER));
assert(box->width && box->height && box->depth);
/* Depth textures use staging unconditionally. */
struct r600_texture *staging;
si_init_temp_resource_from_box(&resource, texture, box, level,
- R600_RESOURCE_FLAG_TRANSFER);
+ SI_RESOURCE_FLAG_TRANSFER);
resource.usage = (usage & PIPE_TRANSFER_READ) ?
PIPE_USAGE_STAGING : PIPE_USAGE_STREAM;
} else {
tex->dcc_separate_buffer = (struct r600_resource*)
si_aligned_buffer_create(sctx->b.b.screen,
- R600_RESOURCE_FLAG_UNMAPPABLE,
+ SI_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
tex->surface.dcc_size,
tex->surface.dcc_alignment);
templ.depth0 = 1;
templ.array_size = 1;
templ.usage = PIPE_USAGE_DEFAULT;
- templ.flags = R600_RESOURCE_FLAG_FORCE_TILING |
- R600_RESOURCE_FLAG_DISABLE_DCC;
+ templ.flags = SI_RESOURCE_FLAG_FORCE_TILING |
+ SI_RESOURCE_FLAG_DISABLE_DCC;
/* The src and dst microtile modes must be the same. */
if (src->surface.micro_tile_mode == RADEON_MICRO_MODE_DISPLAY)
rtex->cmask_buffer = (struct r600_resource *)
si_aligned_buffer_create(&sscreen->b,
- R600_RESOURCE_FLAG_UNMAPPABLE,
+ SI_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
rtex->cmask.size,
rtex->cmask.alignment);
sctx->compute_scratch_buffer = (struct r600_resource*)
si_aligned_buffer_create(&sctx->screen->b,
- R600_RESOURCE_FLAG_UNMAPPABLE,
+ SI_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
scratch_needed, 256);
r600_resource_reference(&sctx->scratch_buffer, NULL);
sctx->scratch_buffer = (struct r600_resource*)
si_aligned_buffer_create(&sctx->screen->b,
- R600_RESOURCE_FLAG_UNMAPPABLE,
+ SI_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
scratch_size, 256);
if (!sctx->scratch_buffer)
sscreen->info.drm_major == 3;
case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
- return R600_MAP_BUFFER_ALIGNMENT;
+ return SI_MAP_BUFFER_ALIGNMENT;
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
return sscreen->info.has_syncobj;
case PIPE_CAP_CONSTBUF0_FLAGS:
- return R600_RESOURCE_FLAG_32BIT;
+ return SI_RESOURCE_FLAG_32BIT;
case PIPE_CAP_NATIVE_FENCE_FD:
return sscreen->info.has_fence_to_handle;
sctx->b.b.stream_uploader = u_upload_create(&sctx->b.b, 1024 * 1024,
0, PIPE_USAGE_STREAM,
- R600_RESOURCE_FLAG_READ_ONLY);
+ SI_RESOURCE_FLAG_READ_ONLY);
if (!sctx->b.b.stream_uploader)
goto fail;
sctx->b.b.const_uploader = u_upload_create(&sctx->b.b, 128 * 1024,
0, PIPE_USAGE_DEFAULT,
- R600_RESOURCE_FLAG_32BIT |
+ SI_RESOURCE_FLAG_32BIT |
(sscreen->cpdma_prefetch_writes_memory ?
- 0 : R600_RESOURCE_FLAG_READ_ONLY));
+ 0 : SI_RESOURCE_FLAG_READ_ONLY));
if (!sctx->b.b.const_uploader)
goto fail;
if (sctx->b.chip_class == CIK) {
sctx->null_const_buf.buffer =
si_aligned_buffer_create(screen,
- R600_RESOURCE_FLAG_32BIT,
+ SI_RESOURCE_FLAG_32BIT,
PIPE_USAGE_DEFAULT, 16,
sctx->screen->info.tcc_cache_line_size);
if (!sctx->null_const_buf.buffer)
#define SI_BIG_ENDIAN 0
#endif
-#define ATI_VENDOR_ID 0x1002
+#define ATI_VENDOR_ID 0x1002
-#define SI_NOT_QUERY 0xffffffff
+#define SI_NOT_QUERY 0xffffffff
/* The base vertex and primitive restart can be any number, but we must pick
* one which will mean "unknown" for the purpose of state tracking and
* the number shouldn't be a commonly-used one. */
-#define SI_BASE_VERTEX_UNKNOWN INT_MIN
-#define SI_RESTART_INDEX_UNKNOWN INT_MIN
-#define SI_NUM_SMOOTH_AA_SAMPLES 8
-#define SI_GS_PER_ES 128
+#define SI_BASE_VERTEX_UNKNOWN INT_MIN
+#define SI_RESTART_INDEX_UNKNOWN INT_MIN
+#define SI_NUM_SMOOTH_AA_SAMPLES 8
+#define SI_GS_PER_ES 128
/* Alignment for optimal CP DMA performance. */
-#define SI_CPDMA_ALIGNMENT 32
+#define SI_CPDMA_ALIGNMENT 32
/* Pipeline & streamout query controls. */
#define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
#define SI_PREFETCH_VS (1 << 5)
#define SI_PREFETCH_PS (1 << 6)
-#define SI_MAX_BORDER_COLORS 4096
-#define SI_MAX_VIEWPORTS 16
-#define SIX_BITS 0x3F
+#define SI_MAX_BORDER_COLORS 4096
+#define SI_MAX_VIEWPORTS 16
+#define SIX_BITS 0x3F
+#define SI_MAP_BUFFER_ALIGNMENT 64
+#define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
+
+#define SI_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
+#define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
+#define SI_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
+#define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
+#define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
+#define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
+#define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
+
+/* Debug flags. */
+enum {
+ /* Shader logging options: */
+ DBG_VS = PIPE_SHADER_VERTEX,
+ DBG_PS = PIPE_SHADER_FRAGMENT,
+ DBG_GS = PIPE_SHADER_GEOMETRY,
+ DBG_TCS = PIPE_SHADER_TESS_CTRL,
+ DBG_TES = PIPE_SHADER_TESS_EVAL,
+ DBG_CS = PIPE_SHADER_COMPUTE,
+ DBG_NO_IR,
+ DBG_NO_TGSI,
+ DBG_NO_ASM,
+ DBG_PREOPT_IR,
+
+ /* Shader compiler options the shader cache should be aware of: */
+ DBG_FS_CORRECT_DERIVS_AFTER_KILL,
+ DBG_UNSAFE_MATH,
+ DBG_SI_SCHED,
+
+ /* Shader compiler options (with no effect on the shader cache): */
+ DBG_CHECK_IR,
+ DBG_NIR,
+ DBG_MONOLITHIC_SHADERS,
+ DBG_NO_OPT_VARIANT,
+
+ /* Information logging options: */
+ DBG_INFO,
+ DBG_TEX,
+ DBG_COMPUTE,
+ DBG_VM,
+
+ /* Driver options: */
+ DBG_FORCE_DMA,
+ DBG_NO_ASYNC_DMA,
+ DBG_NO_WC,
+ DBG_CHECK_VM,
+ DBG_RESERVE_VMID,
+
+ /* 3D engine options: */
+ DBG_SWITCH_ON_EOP,
+ DBG_NO_OUT_OF_ORDER,
+ DBG_NO_DPBB,
+ DBG_NO_DFSM,
+ DBG_DPBB,
+ DBG_DFSM,
+ DBG_NO_HYPERZ,
+ DBG_NO_RB_PLUS,
+ DBG_NO_2D_TILING,
+ DBG_NO_TILING,
+ DBG_NO_DCC,
+ DBG_NO_DCC_CLEAR,
+ DBG_NO_DCC_FB,
+ DBG_NO_DCC_MSAA,
+ DBG_DCC_MSAA,
+ DBG_NO_FMASK,
+
+ /* Tests: */
+ DBG_TEST_DMA,
+ DBG_TEST_VMFAULT_CP,
+ DBG_TEST_VMFAULT_SDMA,
+ DBG_TEST_VMFAULT_SHADER,
+};
+
+#define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
+#define DBG(name) (1ull << DBG_##name)
struct si_compute;
struct hash_table;
shader->bo = (struct r600_resource*)
si_aligned_buffer_create(&sscreen->b,
sscreen->cpdma_prefetch_writes_memory ?
- 0 : R600_RESOURCE_FLAG_READ_ONLY,
+ 0 : SI_RESOURCE_FLAG_READ_ONLY,
PIPE_USAGE_IMMUTABLE,
align(bo_size, SI_CPDMA_ALIGNMENT),
256);
pipe_resource_reference(&sctx->esgs_ring, NULL);
sctx->esgs_ring =
si_aligned_buffer_create(sctx->b.b.screen,
- R600_RESOURCE_FLAG_UNMAPPABLE,
+ SI_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
esgs_ring_size, alignment);
if (!sctx->esgs_ring)
pipe_resource_reference(&sctx->gsvs_ring, NULL);
sctx->gsvs_ring =
si_aligned_buffer_create(sctx->b.b.screen,
- R600_RESOURCE_FLAG_UNMAPPABLE,
+ SI_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
gsvs_ring_size, alignment);
if (!sctx->gsvs_ring)
sctx->scratch_buffer = (struct r600_resource*)
si_aligned_buffer_create(&sctx->screen->b,
- R600_RESOURCE_FLAG_UNMAPPABLE,
+ SI_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
scratch_needed_size, 256);
if (!sctx->scratch_buffer)
* receives the high 13 bits.
*/
sctx->tess_rings = si_aligned_buffer_create(sctx->b.b.screen,
- R600_RESOURCE_FLAG_32BIT,
+ SI_RESOURCE_FLAG_32BIT,
PIPE_USAGE_DEFAULT,
sctx->screen->tess_offchip_ring_size +
sctx->screen->tess_factor_ring_size,
projects / mesa.git / commitdiff