Add $live and $fair cell types, add support for s_eventually keyword

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 06660102bd25bbe4bfc9920ceff74678514afb94..482acd364f821863a791e610c98f7b984d981a9c 100644 (file)
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -84,6 +84,8 @@ std::string AST::type2str(AstNodeType type)
        X(AST_PREFIX)
        X(AST_ASSERT)
        X(AST_ASSUME)
+       X(AST_LIVE)
+       X(AST_FAIR)
        X(AST_COVER)
        X(AST_FCALL)
        X(AST_TO_BITS)

diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index 0b9116d39588e7b45d63c8c1f2d2b96fd2823c53..bddda9667d1a1d9b0f8465e6d428e1a151192313 100644 (file)
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -65,6 +65,8 @@ namespace AST
                AST_PREFIX,
                AST_ASSERT,
                AST_ASSUME,
+               AST_LIVE,
+               AST_FAIR,
                AST_COVER,
 
                AST_FCALL,

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index bdac4de00849dbcc9f2ad7ae8a5279de38235d11..78e83e038615466ecdbb5830f023167eb6d3557e 100644 (file)
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -1336,10 +1336,15 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
        // generate $assert cells
        case AST_ASSERT:
        case AST_ASSUME:
+       case AST_LIVE:
+       case AST_FAIR:
        case AST_COVER:
                {
-                       const char *celltype = "$assert";
+                       const char *celltype = nullptr;
+                       if (type == AST_ASSERT) celltype = "$assert";
                        if (type == AST_ASSUME) celltype = "$assume";
+                       if (type == AST_LIVE) celltype = "$live";
+                       if (type == AST_FAIR) celltype = "$fair";
                        if (type == AST_COVER) celltype = "$cover";
 
                        log_assert(children.size() == 2);

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index f7fcbc479b093fd176d4a8270d174ef153a2dbd7..28c9945abf420fd1f94ca583c3201d1e4548499a 100644 (file)
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -1400,7 +1400,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
        }
 skip_dynamic_range_lvalue_expansion:;
 
-       if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME || type == AST_COVER) && current_block != NULL)
+       if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME || type == AST_LIVE || type == AST_FAIR || type == AST_COVER) && current_block != NULL)
        {
                std::stringstream sstr;
                sstr << "$formal$" << filename << ":" << linenum << "$" << (autoidx++);
@@ -1462,7 +1462,7 @@ skip_dynamic_range_lvalue_expansion:;
                goto apply_newNode;
        }
 
-       if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME || type == AST_COVER) && children.size() == 1)
+       if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME || type == AST_LIVE || type == AST_FAIR || type == AST_COVER) && children.size() == 1)
        {
                children.push_back(mkconst_int(1, false, 1));
                did_something = true;

diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index 091c1a02944647d92c0588a301df102f079e7da8..885332b762d38d443f877e48c797e6d417aa2631 100644 (file)
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -191,6 +191,9 @@ YOSYS_NAMESPACE_END
 "logic"      { SV_KEYWORD(TOK_REG); }
 "bit"        { SV_KEYWORD(TOK_REG); }
 
+"eventually"   { if (formal_mode) return TOK_EVENTUALLY; SV_KEYWORD(TOK_EVENTUALLY); }
+"s_eventually" { if (formal_mode) return TOK_EVENTUALLY; SV_KEYWORD(TOK_EVENTUALLY); }
+
 "input"   { return TOK_INPUT; }
 "output"  { return TOK_OUTPUT; }
 "inout"   { return TOK_INOUT; }

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 9b24986941f1302980f3a460813178e7d4304718..60b1ecffd13a370b3eb002371ef2015f87ab0807 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -116,7 +116,7 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 %token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED
 %token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_ASSERT TOK_ASSUME
 %token TOK_RESTRICT TOK_COVER TOK_PROPERTY TOK_ENUM TOK_TYPEDEF
-%token TOK_RAND TOK_CONST TOK_CHECKER TOK_ENDCHECKER
+%token TOK_RAND TOK_CONST TOK_CHECKER TOK_ENDCHECKER TOK_EVENTUALLY
 %token TOK_INCREMENT TOK_DECREMENT TOK_UNIQUE TOK_PRIORITY
 
 %type <ast> range range_or_multirange  non_opt_range non_opt_multirange range_or_signed_int
@@ -1030,6 +1030,12 @@ assert:
        TOK_ASSUME '(' expr ')' ';' {
                ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $3));
        } |
+       TOK_ASSERT '(' TOK_EVENTUALLY expr ')' ';' {
+               ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $4));
+       } |
+       TOK_ASSUME '(' TOK_EVENTUALLY expr ')' ';' {
+               ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $4));
+       } |
        TOK_COVER '(' expr ')' ';' {
                ast_stack.back()->children.push_back(new AstNode(AST_COVER, $3));
        } |
@@ -1044,6 +1050,12 @@ assert:
                        delete $3;
                else
                        ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $3));
+       } |
+       TOK_RESTRICT '(' TOK_EVENTUALLY expr ')' ';' {
+               if (norestrict_mode)
+                       delete $4;
+               else
+                       ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $4));
        };
 
 assert_property:
@@ -1053,6 +1065,12 @@ assert_property:
        TOK_ASSUME TOK_PROPERTY '(' expr ')' ';' {
                ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $4));
        } |
+       TOK_ASSERT TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
+               ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $5));
+       } |
+       TOK_ASSUME TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
+               ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $5));
+       } |
        TOK_COVER TOK_PROPERTY '(' expr ')' ';' {
                ast_stack.back()->children.push_back(new AstNode(AST_COVER, $4));
        } |
@@ -1061,6 +1079,12 @@ assert_property:
                        delete $4;
                else
                        ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $4));
+       } |
+       TOK_RESTRICT TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
+               if (norestrict_mode)
+                       delete $5;
+               else
+                       ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $5));
        };
 
 simple_behavioral_stmt:

diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 8f31d01724f11d045a1aca24665ec690641504d6..c43f685acf571d5b3f5ff3e6ad9557b8e7050fb4 100644 (file)
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -116,6 +116,8 @@ struct CellTypes
 
                setup_type("$assert", {A, EN}, pool<RTLIL::IdString>(), true);
                setup_type("$assume", {A, EN}, pool<RTLIL::IdString>(), true);
+               setup_type("$live", {A, EN}, pool<RTLIL::IdString>(), true);
+               setup_type("$fair", {A, EN}, pool<RTLIL::IdString>(), true);
                setup_type("$cover", {A, EN}, pool<RTLIL::IdString>(), true);
                setup_type("$initstate", pool<RTLIL::IdString>(), {Y}, true);
                setup_type("$anyconst", pool<RTLIL::IdString>(), {Y}, true);

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 978a7a53739c688b8642c8031496766c6207856e..6ce3f13767c6c46ddc3e970bb3ed0f51be15619f 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1026,7 +1026,7 @@ namespace {
                                return;
                        }
 
-                       if (cell->type.in("$assert", "$assume", "$cover")) {
+                       if (cell->type.in("$assert", "$assume", "$live", "$fair", "$cover")) {
                                port("\\A", 1);
                                port("\\EN", 1);
                                check_expected();
@@ -1819,6 +1819,22 @@ RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a
        return cell;
 }
 
+RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en)
+{
+       RTLIL::Cell *cell = addCell(name, "$live");
+       cell->setPort("\\A", sig_a);
+       cell->setPort("\\EN", sig_en);
+       return cell;
+}
+
+RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en)
+{
+       RTLIL::Cell *cell = addCell(name, "$fair");
+       cell->setPort("\\A", sig_a);
+       cell->setPort("\\EN", sig_en);
+       return cell;
+}
+
 RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en)
 {
        RTLIL::Cell *cell = addCell(name, "$cover");

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 7a6f5717dafa6339dd44f2b446c1498fe3c2e614..ab877125627f7b0ddee0907a1ab9daf2f02d9068 100644 (file)
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -1007,6 +1007,8 @@ public:
        RTLIL::Cell* addTribuf (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y);
        RTLIL::Cell* addAssert (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en);
        RTLIL::Cell* addAssume (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en);
+       RTLIL::Cell* addLive   (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en);
+       RTLIL::Cell* addFair   (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en);
        RTLIL::Cell* addCover  (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en);
        RTLIL::Cell* addEquiv  (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y);
 

diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex
index 7686f596380a5e61c1dfefa24f148c96b2408dd9..b2ba1fd8822b717e66738d3f22b060cce9531502 100644 (file)
--- a/manual/CHAPTER_CellLib.tex
+++ b/manual/CHAPTER_CellLib.tex
@@ -421,7 +421,7 @@ pass. The combinatorial logic cells can be mapped to physical cells from a Liber
 using the {\tt abc} pass.
 
 \begin{fixme}
-Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$cover}, {\tt \$equiv}, {\tt \$initstate}, {\tt \$anyconst}, and {\tt \$anyseq} cells.
+Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$live}, {\tt \$fair}, {\tt \$cover}, {\tt \$equiv}, {\tt \$initstate}, {\tt \$anyconst}, and {\tt \$anyseq} cells.
 \end{fixme}
 
 \begin{fixme}

diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 3534cbcdb2e2ece0dd429701b4a98db818d3d240..d71e9c574bdd3af9bcb91f570488b587f7e7596a 100644 (file)
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -313,7 +313,7 @@ bool set_keep_assert(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod)
        if (cache.count(mod) == 0)
                for (auto c : mod->cells()) {
                        RTLIL::Module *m = mod->design->module(c->type);
-                       if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in("$assert", "$assume", "$cover"))
+                       if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in("$assert", "$assume", "$live", "$fair", "$cover"))
                                return cache[mod] = true;
                }
        return cache[mod];

diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 65944caec9659e2acc9866bad3ed8c0e634c39f5..c426c4bf26a39fd32dfa2ab92d4a62f447d758c7 100644 (file)
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -64,7 +64,7 @@ struct keep_cache_t
 
        bool query(Cell *cell)
        {
-               if (cell->type.in("$memwr", "$meminit", "$assert", "$assume", "$cover"))
+               if (cell->type.in("$memwr", "$meminit", "$assert", "$assume", "$live", "$fair", "$cover"))
                        return true;
 
                if (cell->has_keep_attr())

diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc
index 049c20533318a186ddc8e463ac796fcd89bda1ac..47b6bdf23468c2e982384bc2a0e65bc52d687b6b 100644 (file)
--- a/passes/tests/test_cell.cc
+++ b/passes/tests/test_cell.cc
@@ -852,8 +852,6 @@ struct TestCellPass : public Pass {
 
                // cell_types["$slice"] = "A";
                // cell_types["$concat"] = "A";
-               // cell_types["$assert"] = "A";
-               // cell_types["$assume"] = "A";
 
                cell_types["$lut"] = "*";
                cell_types["$sop"] = "*";

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index d0abd3b34a80865a100283bae3f83c680f1b6596..276503fe88437a360f4cae7e2bc9a34cd2f34ca8 100644 (file)
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1305,6 +1305,22 @@ endmodule
 
 // --------------------------------------------------------
 
+module \$live (A, EN);
+
+input A, EN;
+
+endmodule
+
+// --------------------------------------------------------
+
+module \$fair (A, EN);
+
+input A, EN;
+
+endmodule
+
+// --------------------------------------------------------
+
 module \$cover (A, EN);
 
 input A, EN;