(no commit message)

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 52cc8cec05e81cebee9f65b840029d0e4c5e3dfe..3275ba06cae0c2db29964d54af76bf48ba16ccf9 100644 (file)
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -267,7 +267,8 @@ considered.
 * **CTR-test=0, CTi=1**: CTR decrements on a per-element basis
   if `BO[2]` is zero and a masked-out element is skipped
   (`sz=0` and predicate bit is zero). This one special case is the
-  **opposite** of other combinations.
+  **opposite** of other combinations, as well as being
+  completely different from normal SVP64 `sz=0` behaviour)
 * **CTR-test=1, CTi=0**: CTR decrements on a per-element basis
   if `BO[2]` is zero and the Condition Test succeeds.
   Masked-out elements when `sz=0` are skipped.
@@ -275,7 +276,12 @@ considered.
   if `BO[2]` is zero and the Condition Test *fails*.
   Masked-out elements when `sz=0` are skipped.
 
-Note that, interestingly, due to the side-effects of `VLSET` mode
+`CTR-test=0, CTi=1, sz=0` requires special emphasis because it is the
+only time in the entirety of SVP64 that has side-effects when
+a predicate mask bit is clear.  **All** other SVP64 operations
+entirely skip an element when sz=0 and a predicate mask bit is zero.
+
+Interestingly, due to the side-effects of `VLSET` mode
 it is actually useful to use Branch Conditional even
 to perform no actual branch operation, i.e to point to the instruction
 after the branch. Truncation of VL would thus conditionally occur yet control