n1 = mask[1] & (mode[1] == creg[1])
n2 = mask[2] & (mode[2] == creg[2])
n3 = mask[3] & (mode[3] == creg[3])
- result = n0|n1|n2|n3 if M else n0&n1&n2&n3
+ n = (n0||n1||n2||n3) & mask
+ result = (n != 0) if M else (n == mask)
RT[63] = result # MSB0 numbering, 63 is LSB
If Rc:
CR0 = analyse(RT)
n3 = mask[3] & (mode[3] == creg[3])
BF = BT[2:4] # select CR
bit = BT[0:1] # select bit of CR
- result = n0|n1|n2|n3 if M else n0&n1&n2&n3
+ n = (n0||n1||n2||n3) & mask
+ result = (n != 0) if M else (n == mask)
CR{BF}[bit] = result
When used with SVP64 Prefixing this is a [[sv/cr_ops]] SVP64
n2 = mask[2] & (mode[2] == creg[2])
n3 = mask[3] & (mode[3] == creg[3])
# OR or AND to a single bit
- result = n0|n1|n2|n3 if M else n0&n1&n2&n3
+ n = (n0||n1||n2||n3) & mask
+ result = (n != 0) if M else (n == mask)
if RT.isvec:
# TODO: RT.elwidth override to be also added here
# note, yes, really, the CR's elwidth field determines
idx, boff = 0, i
iregs[RT+idx][60-boff*4:63-boff*4] = result
-
-
# v3.1 setbc instructions
There are additional setb conditional instructions in v3.1 (p129)