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diff --git a/simple_v_extension/sv_prefix_proposal/discussion.rst b/simple_v_extension/sv_prefix_proposal/discussion.rst
index 2d166b520a832ace344e2c6f5f75fb873f770db9..299832af8a15411d67b0491a7f61d2ad62f1a193 100644 (file)
--- a/simple_v_extension/sv_prefix_proposal/discussion.rst
+++ b/simple_v_extension/sv_prefix_proposal/discussion.rst
@@ -264,24 +264,24 @@ experiment 1:
 
 experiment 2:
 
-+-----------+-------------+------------+--------------+------------+----------------------+
-| VLtyp[11] | VLtyp[10:6] | VLtyp[5]   | VLtyp[4:3]   | VLtyp[2:0] | comment              |
-+-----------+-------------+------------+--------------+------------+----------------------+
-| 0         |  00000      | 0            00           |  000       | no change to VL/MVL  |
-+-----------+-------------+---------------------------+------------+----------------------+
-| 0         |  imm        | 000                       |  rs'!=0    | sv.setvl immed mode  |
-+-----------+-------------+---------------------------+------------+----------------------+
-| 0         |  imm        | rd'!=0                    |  000       | not sure. reserved?  |
-+-----------+-------------+---------------------------+------------+----------------------+
-| 0         |  imm        | rd'!=0                    |  rs'!=0    | sv.setvl rd, rs, MVL |
-+-----------+-------------+------------+--------------+------------+----------------------+
-| 1         |  imm        | 0          |  00             000       | set MVL immed        |
-+-----------+-------------+------------+---------------------------+----------------------+
-| 1         |  imm        | 0          |  rd[4:0]                  | sv.setvl rd, immed   |
-+-----------+-------------+------------+---------------------------+----------------------+
-| 1         |  imm        | 1          |  00             000       | something. reserved? |
-+-----------+-------------+------------+---------------------------+----------------------+
-| 1         |  imm        | 1          |  rs1[4:0]                 | set MVL rs1?         |
-+-----------+-------------+------------+---------------------------+----------------------+
-
-
++-----------+-------------+------------+--------------+------------+-----------------------------------------------+
+| VLtyp[11] | VLtyp[10:6] | VLtyp[5]   | VLtyp[4:3]   | VLtyp[2:0] | comment                                       |
++-----------+-------------+------------+--------------+------------+-----------------------------------------------+
+| 0         |  00000      | 0            00           |  000       | no change to VL/MVL                           |
++-----------+-------------+---------------------------+------------+-----------------------------------------------+
+| 0         |  imm        | 000                       |  rs'!=0    | MVL = imm; vl = min(r[rs'], MVL)              |
++-----------+-------------+---------------------------+------------+-----------------------------------------------+
+| 0         |  imm        | rd'!=0                    |  000       | MVL = imm; vl = MVL; r[rd'] = vl              |
++-----------+-------------+---------------------------+------------+-----------------------------------------------+
+| 0         |  imm        | rd'!=0                    |  rs'!=0    | MVL = imm; vl = min(r[rs'], MVL); r[rd'] = vl |
++-----------+-------------+------------+--------------+------------+-----------------------------------------------+
+| 1         |  imm        | 0          |  00             000       | MVL = imm; vl = MVL;                          |
++-----------+-------------+------------+---------------------------+-----------------------------------------------+
+| 1         |  imm        | 0          |  rd[4:0]                  | MVL = imm; vl = MVL; r[rd] = vl               |
++-----------+-------------+------------+---------------------------+-----------------------------------------------+
+| 1         |  imm        | 1          |  00             000       | reserved                                      |
++-----------+-------------+------------+---------------------------+-----------------------------------------------+
+| 1         |  imm        | 1          |  rs1[4:0]                 | MVL = imm; vl = min(r[rs], MVL)               |
++-----------+-------------+------------+---------------------------+-----------------------------------------------+
+
+interestingly, "VLtyp[11] = 0" fits the sv.setvl pseudcode really well.