}
assert(this->exec_size != 0);
+ for (int i = 0; i < sources; ++i) {
+ switch (this->src[i].file) {
+ case BAD_FILE:
+ this->src[i].effective_width = 8;
+ break;
+ case GRF:
+ case HW_REG:
+ assert(this->src[i].width > 0);
+ if (this->src[i].width == 1) {
+ this->src[i].effective_width = this->exec_size;
+ } else {
+ this->src[i].effective_width = this->src[i].width;
+ }
+ break;
+ case IMM:
+ case UNIFORM:
+ this->src[i].effective_width = this->exec_size;
+ break;
+ default:
+ unreachable("Invalid source register file");
+ }
+ }
+ this->dst.effective_width = this->exec_size;
+
this->conditional_mod = BRW_CONDITIONAL_NONE;
/* This will be the case for almost all instructions. */
* dealing with whole registers. If this ever changes, we can deal
* with it later.
*/
- int size = src[i].effective_width(this) * type_sz(src[i].type);
+ int size = src[i].effective_width * type_sz(src[i].type);
assert(size % 32 == 0);
inst->regs_written += (size + 31) / 32;
}
stride == r.stride);
}
-uint8_t
-fs_reg::effective_width(const fs_visitor *v) const
-{
- switch (this->file) {
- case BAD_FILE:
- return 8;
- case UNIFORM:
- case IMM:
- assert(this->width == 1);
- return v->dispatch_width;
- case GRF:
- case HW_REG:
- assert(this->width > 1 && this->width <= v->dispatch_width);
- assert(this->width % 8 == 0);
- return this->width;
- case MRF:
- unreachable("MRF registers cannot be used as sources");
- default:
- unreachable("Invalid register file");
- }
-}
-
fs_reg &
fs_reg::apply_stride(unsigned stride)
{
fs_reg dst = inst->dst;
for (int i = 0; i < inst->sources; i++) {
- dst.width = inst->src[i].effective_width(this);
+ dst.width = inst->src[i].effective_width;
dst.type = inst->src[i].type;
if (inst->src[i].file == BAD_FILE) {
if (inst->src[i].negate || inst->src[i].abs)
continue;
+ fs_reg val = entry->src;
+ val.effective_width = inst->src[i].effective_width;
+
switch (inst->opcode) {
case BRW_OPCODE_MOV:
- inst->src[i] = entry->src;
+ inst->src[i] = val;
progress = true;
break;
case BRW_OPCODE_SHR:
case BRW_OPCODE_SUBB:
if (i == 1) {
- inst->src[i] = entry->src;
+ inst->src[i] = val;
progress = true;
}
break;
case BRW_OPCODE_XOR:
case BRW_OPCODE_ADDC:
if (i == 1) {
- inst->src[i] = entry->src;
+ inst->src[i] = val;
progress = true;
} else if (i == 0 && inst->src[1].file != IMM) {
/* Fit this constant in by commuting the operands.
inst->src[1].type == BRW_REGISTER_TYPE_UD))
break;
inst->src[0] = inst->src[1];
- inst->src[1] = entry->src;
+ inst->src[1] = val;
progress = true;
}
break;
case BRW_OPCODE_CMP:
case BRW_OPCODE_IF:
if (i == 1) {
- inst->src[i] = entry->src;
+ inst->src[i] = val;
progress = true;
} else if (i == 0 && inst->src[1].file != IMM) {
enum brw_conditional_mod new_cmod;
* flipping the test
*/
inst->src[0] = inst->src[1];
- inst->src[1] = entry->src;
+ inst->src[1] = val;
inst->conditional_mod = new_cmod;
progress = true;
}
case BRW_OPCODE_SEL:
if (i == 1) {
- inst->src[i] = entry->src;
+ inst->src[i] = val;
progress = true;
} else if (i == 0 && inst->src[1].file != IMM) {
inst->src[0] = inst->src[1];
- inst->src[1] = entry->src;
+ inst->src[1] = val;
/* If this was predicated, flipping operands means
* we also need to flip the predicate.
assert(i == 0);
if (inst->src[0].fixed_hw_reg.dw1.f != 0.0f) {
inst->opcode = BRW_OPCODE_MOV;
- inst->src[0] = entry->src;
+ inst->src[0] = val;
inst->src[0].fixed_hw_reg.dw1.f = 1.0f / inst->src[0].fixed_hw_reg.dw1.f;
progress = true;
}
break;
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
- inst->src[i] = entry->src;
+ inst->src[i] = val;
progress = true;
break;
inst->dst.file == GRF) {
int offset = 0;
for (int i = 0; i < inst->sources; i++) {
- int regs_written = ((inst->src[i].effective_width(this) *
+ int regs_written = ((inst->src[i].effective_width *
type_sz(inst->src[i].type)) + 31) / 32;
if (inst->src[i].file == GRF) {
acp_entry *entry = ralloc(copy_prop_ctx, acp_entry);
entry->dst = inst->dst;
entry->dst.reg_offset = offset;
- entry->dst.width = inst->src[i].effective_width(this);
+ entry->dst.width = inst->src[i].effective_width;
entry->src = inst->src[i];
entry->regs_written = regs_written;
entry->opcode = inst->opcode;