# endif
bfd_boolean
-arm_is_eabi(void)
+arm_is_eabi (void)
{
return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
}
may differ from:
...
label:
- <insn>
-*/
+ <insn> */
symbolS * last_label_seen;
static int label_is_thumb_function_name = FALSE;
/* State variables for IT block handling. */
static bfd_boolean current_it_mask = 0;
static int current_cc;
-
\f
/* Pure syntax. */
}
else
return FAIL;
-
+
*ccp = str;
-
+
return SUCCESS;
}
if (reg->neon)
atype = *reg->neon;
-
+
if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
{
if ((atype.defined & NTA_HASTYPE) != 0)
atype.defined |= NTA_HASTYPE;
atype.eltype = parsetype;
}
-
+
if (skip_past_char (&str, '[') == SUCCESS)
{
if (type != REG_TYPE_VFD)
first_error (_("only D registers may be indexed"));
return FAIL;
}
-
+
if ((atype.defined & NTA_HASINDEX) != 0)
{
first_error (_("can't change index for operand"));
atype.index = exp.X_add_number;
}
}
-
+
if (typeinfo)
*typeinfo = atype;
-
+
if (rtype)
*rtype = type;
-
+
*ccp = str;
-
+
return reg->number;
}
register (e.g. Neon double or quad reg when either has been requested).
- If this is a Neon vector type with additional type information, fill
in the struct pointed to by VECTYPE (if non-NULL).
- This function will fault on encountering a scalar.
-*/
+ This function will fault on encountering a scalar. */
static int
arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
int reg;
char *str = *ccp;
struct neon_typed_alias atype;
-
+
reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
-
+
if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
return FAIL;
-
+
if (atype.index == NEON_ALL_LANES)
{
first_error (_("scalar must have an index"));
first_error (_("scalar index out of range"));
return FAIL;
}
-
+
if (type)
*type = atype.eltype;
-
+
*ccp = str;
-
+
return reg * 16 + atype.index;
}
regtype = REG_TYPE_VFS;
max_regs = 32;
break;
-
+
case REGLIST_VFP_D:
regtype = REG_TYPE_VFD;
break;
-
+
case REGLIST_NEON_D:
regtype = REG_TYPE_NDQ;
break;
first_error (_(reg_expected_msgs[regtype]));
return FAIL;
}
-
+
if (new_base >= max_regs)
{
first_error (_("register out of range in list"));
return FAIL;
}
-
+
/* Note: a value of 2 * n is returned for the register Q<n>. */
if (regtype == REG_TYPE_NQ)
{
{
if (!a && !b)
return 1;
-
+
if (!a || !b)
return 0;
if (a->defined != b->defined)
return 0;
-
+
if ((a->defined & NTA_HASTYPE) != 0
&& (a->eltype.type != b->eltype.type
|| a->eltype.size != b->eltype.size))
if ((a->defined & NTA_HASINDEX) != 0
&& (a->index != b->index))
return 0;
-
+
return 1;
}
const char *const incr_error = "register stride must be 1 or 2";
const char *const type_error = "mismatched element/structure types in list";
struct neon_typed_alias firsttype;
-
+
if (skip_past_char (&ptr, '{') == SUCCESS)
leading_brace = 1;
-
+
do
{
struct neon_typed_alias atype;
first_error (_(reg_expected_msgs[rtype]));
return FAIL;
}
-
+
if (base_reg == -1)
{
base_reg = getreg;
first_error (_(type_error));
return FAIL;
}
-
+
/* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
modes. */
if (ptr[0] == '-')
count += hireg + dregs - getreg;
continue;
}
-
+
/* If we're using Q registers, we can't use [] or [n] syntax. */
if (rtype == REG_TYPE_NQ)
{
count += 2;
continue;
}
-
+
if ((atype.defined & NTA_HASINDEX) != 0)
{
if (lane == -1)
count++;
}
while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
-
+
/* No lane set by [x]. We must be interleaving structures. */
if (lane == -1)
lane = NEON_INTERLEAVE_LANES;
-
+
/* Sanity check. */
if (lane == -1 || base_reg == -1 || count < 1 || count > 4
|| (count > 1 && reg_incr == -1))
first_error (_("expected }"));
return FAIL;
}
-
+
if (reg_incr == -1)
reg_incr = 1;
*pbase = base_reg;
*str = ptr;
-
+
return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
}
if (hash_insert (arm_reg_hsh, name, (PTR) new))
abort ();
-
+
return new;
}
struct neon_typed_alias *atype)
{
struct reg_entry *reg = insert_reg_alias (str, number, type);
-
+
if (!reg)
{
first_error (_("attempt to redefine typed alias"));
return;
}
-
+
if (atype)
{
reg->neon = xmalloc (sizeof (struct neon_typed_alias));
foo .req r0
Foo .req r1
The second .req creates the "Foo" alias but then fails to create
- the artifical FOO alias because it has already been created by the
+ the artificial FOO alias because it has already been created by the
first .req. */
if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
return TRUE;
These typed registers can be used instead of the types specified after the
Neon mnemonic, so long as all operands given have types. Types can also be
specified directly, e.g.:
- vadd d0.s32, d1.s32, d2.s32
-*/
+ vadd d0.s32, d1.s32, d2.s32 */
static int
create_neon_reg_alias (char *newname, char *p)
struct neon_typed_alias typeinfo;
char *namebuf, *nameend;
int namelen;
-
+
typeinfo.defined = 0;
typeinfo.eltype.type = NT_invtype;
typeinfo.eltype.size = -1;
typeinfo.index = -1;
-
+
nameend = p;
-
+
if (strncmp (p, " .dn ", 5) == 0)
basetype = REG_TYPE_VFD;
else if (strncmp (p, " .qn ", 5) == 0)
basetype = REG_TYPE_NQ;
else
return 0;
-
+
p += 5;
-
+
if (*p == '\0')
return 0;
-
+
basereg = arm_reg_parse_multi (&p);
if (basereg && basereg->type != basetype)
as_bad (_("can't redefine the type of a register alias"));
return 0;
}
-
+
typeinfo.defined |= NTA_HASTYPE;
if (ntype.elems != 1)
{
}
typeinfo.eltype = ntype.el[0];
}
-
+
if (skip_past_char (&p, '[') == SUCCESS)
{
expressionS exp;
/* We got a scalar index. */
-
+
if (typeinfo.defined & NTA_HASINDEX)
{
as_bad (_("can't redefine the index of a scalar alias"));
return 0;
}
-
+
my_get_expression (&exp, &p, GE_NO_PREFIX);
-
+
if (exp.X_op != O_constant)
{
as_bad (_("scalar index must be constant"));
return 0;
}
-
+
typeinfo.defined |= NTA_HASINDEX;
typeinfo.index = exp.X_add_number;
-
+
if (skip_past_char (&p, ']') == FAIL)
{
as_bad (_("expecting ]"));
namebuf = alloca (namelen + 1);
strncpy (namebuf, newname, namelen);
namebuf[namelen] = '\0';
-
+
insert_neon_reg_alias (namebuf, basereg->number, basetype,
typeinfo.defined != 0 ? &typeinfo : NULL);
-
+
/* Insert name in all uppercase. */
for (p = namebuf; *p; p++)
*p = TOUPPER (*p);
-
+
if (strncmp (namebuf, newname, namelen))
insert_neon_reg_alias (namebuf, basereg->number, basetype,
typeinfo.defined != 0 ? &typeinfo : NULL);
-
+
/* Insert name in all lowercase. */
for (p = namebuf; *p; p++)
*p = TOLOWER (*p);
-
+
if (strncmp (namebuf, newname, namelen))
insert_neon_reg_alias (namebuf, basereg->number, basetype,
typeinfo.defined != 0 ? &typeinfo : NULL);
-
+
return 1;
}
/* Also locate the all upper case and all lower case versions.
Do not complain if we cannot find one or the other as it
was probably deleted above. */
-
+
nbuf = strdup (name);
for (p = nbuf; *p; p++)
*p = TOUPPER (*p);
}
/* Add the literal in the global 'inst'
- structure to the relevent literal pool. */
+ structure to the relevant literal pool. */
static int
add_to_lit_pool (void)
if (unwind.personality_index >= 0 && unwind.personality_index < 3
&& !(marked_pr_dependency & (1 << unwind.personality_index)))
{
- static const char *const name[] = {
- "__aeabi_unwind_cpp_pr0",
- "__aeabi_unwind_cpp_pr1",
- "__aeabi_unwind_cpp_pr2"
- };
+ static const char *const name[] =
+ {
+ "__aeabi_unwind_cpp_pr0",
+ "__aeabi_unwind_cpp_pr1",
+ "__aeabi_unwind_cpp_pr2"
+ };
symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
marked_pr_dependency |= 1 << unwind.personality_index;
|| !(mask & (1 << reg)))
{
/* We found an unsaved reg. Generate opcodes to save the
- preceeding block. */
+ preceding block. */
if (reg != hi_reg)
{
if (reg == 9)
#ifdef TE_PE
static void
-pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
+pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
{
expressionS exp;
}
else
return FAIL;
-
+
*str = ptr;
return SUCCESS;
char *fpnum;
LITTLENUM_TYPE words[MAX_LITTLENUMS];
int found_fpchar = 0;
-
+
skip_past_char (&str, '#');
-
+
/* We must not accidentally parse an integer as a floating-point number. Make
sure that the value we parse is not an integer by checking for special
characters '.' or 'e'.
if (!found_fpchar)
return FAIL;
}
-
+
if ((str = atof_ieee (str, 's', words)) != NULL)
{
unsigned fpword = 0;
int i;
-
+
/* Our FP word must be 32 bits (single-precision FP). */
for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
{
fpword <<= LITTLENUM_NUMBER_OF_BITS;
fpword |= words[i];
}
-
+
if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
*immed = fpword;
else
return FAIL;
*ccp = str;
-
+
return SUCCESS;
}
-
+
return FAIL;
}
{
int length = strlen (group_reloc_table[i].name);
- if (strncasecmp (group_reloc_table[i].name, *str, length) == 0 &&
- (*str)[length] == ':')
+ if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
+ && (*str)[length] == ':')
{
*out = &group_reloc_table[i];
*str += (length + 1);
p--;
}
- if (group_relocations &&
- ((*p == '#' && *(p + 1) == ':') || *p == ':'))
-
+ if (group_relocations
+ && ((*p == '#' && *(p + 1) == ':') || *p == ':'))
{
struct group_reloc_table_entry *entry;
parse_half (char **str)
{
char * p;
-
+
p = *str;
skip_past_char (&p, '#');
- if (strncasecmp (p, ":lower16:", 9) == 0)
+ if (strncasecmp (p, ":lower16:", 9) == 0)
inst.reloc.type = BFD_RELOC_ARM_MOVW;
else if (strncasecmp (p, ":upper16:", 9) == 0)
inst.reloc.type = BFD_RELOC_ARM_MOVT;
if (inst.reloc.type != BFD_RELOC_UNUSED)
{
p += 9;
- skip_whitespace(p);
+ skip_whitespace (p);
}
if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
inst.error = _("',' expected");
return FAIL;
}
-
+
if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
{
inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
enum arm_reg_type rtype;
char *ptr = *str;
struct neon_type_el optype;
-
+
if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
{
/* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
if (skip_past_comma (&ptr) == FAIL)
goto wanted_comma;
-
+
if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
goto wanted_arm;
-
+
inst.operands[i].reg = val;
inst.operands[i].isreg = 1;
inst.operands[i].present = 1;
/* Cases 0, 1, 2, 3, 5 (D only). */
if (skip_past_comma (&ptr) == FAIL)
goto wanted_comma;
-
+
inst.operands[i].reg = val;
inst.operands[i].isreg = 1;
inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
inst.operands[i].isvec = 1;
inst.operands[i].vectype = optype;
inst.operands[i].present = 1;
-
+
if (skip_past_comma (&ptr) == SUCCESS)
{
/* Case 15. */
inst.operands[i].reg = val;
inst.operands[i].isreg = 1;
inst.operands[i++].present = 1;
-
+
if (skip_past_comma (&ptr) == FAIL)
goto wanted_comma;
-
+
if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
goto wanted_arm;
-
+
inst.operands[i].reg = val;
inst.operands[i].isreg = 1;
inst.operands[i++].present = 1;
inst.operands[i].reg = val;
inst.operands[i].isreg = 1;
inst.operands[i++].present = 1;
-
+
if (skip_past_comma (&ptr) == FAIL)
goto wanted_comma;
-
+
if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
{
/* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
inst.operands[i].reg = val;
inst.operands[i].isreg = 1;
inst.operands[i++].present = 1;
-
+
if (skip_past_comma (&ptr) == FAIL)
goto wanted_comma;
-
+
if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
== FAIL)
{
inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
inst.operands[i].vectype = optype;
inst.operands[i].present = 1;
-
+
if (rtype == REG_TYPE_VFS)
{
/* Case 14. */
*str = ptr;
return SUCCESS;
- wanted_comma:
+ wanted_comma:
first_error (_("expected comma"));
return FAIL;
-
- wanted_arm:
+
+ wanted_arm:
first_error (_(reg_expected_msgs[REG_TYPE_RN]));
return FAIL;
}
if (!backtrack_pos)
{
/* The parse routine should already have set inst.error, but set a
- defaut here just in case. */
+ default here just in case. */
if (!inst.error)
inst.error = _("syntax error");
return FAIL;
case VFP_REG_Dd:
inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
break;
-
+
case VFP_REG_Dn:
inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
break;
-
+
case VFP_REG_Dm:
inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
break;
return 0;
}
-/* Functions for instruction encoding, sorted by subarchitecture.
+/* Functions for instruction encoding, sorted by sub-architecture.
First some generics; their names are taken from the conventional
bit positions for register arguments in ARM format instructions. */
MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
- Result unpredicatable if Rd or Rn is R15. */
+ Result unpredictable if Rd or Rn is R15. */
static void
do_co_reg2c (void)
if (!inst.operands[1].present)
inst.operands[1].reg = inst.operands[0].reg + 1;
-
+
if (inst.instruction & LOAD_BIT)
{
/* encode_arm_addr_mode_3 will diagnose overlap between the base
do_vfp_nsyn_opcode ("fmrx");
else
return FAIL;
-
+
return SUCCESS;
}
encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
vfp_conv (32);
}
-
\f
/* FPA instructions. Also in a logical order. */
encode_arm_cp_address (2, TRUE, TRUE, 0);
}
-
\f
/* iWMMXt instructions: strictly in alphabetical order. */
case 4:
case 5:
case 6:
- case 7:
+ case 7:
/* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
inst.operands[2].imm = 16;
inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
if (load)
inst.instruction |= 0x00100000;
- mask = ffs(mask) - 1;
+ mask = ffs (mask) - 1;
mask <<= 12;
}
else if (writeback)
if (inst.instruction < 0xffff)
inst.instruction = THUMB_OP32 (inst.instruction);
- encode_thumb2_ldmstm(inst.operands[0].reg, inst.operands[1].imm,
- inst.operands[0].writeback);
+ encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm,
+ inst.operands[0].writeback);
}
}
else
if (inst.operands[1].immisreg)
{
inst.instruction = THUMB_OP16 (opcode);
- /* [Rn, Ri] */
+ /* [Rn, Rik] */
if (Rn <= 7 && inst.operands[1].imm <= 7)
goto op16;
}
inst.instruction = THUMB_OP16 (inst.instruction);
goto op16;
}
-
+
inst.instruction = THUMB_OP16 (inst.instruction);
if (!inst.operands[1].isreg)
if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
inst.instruction |= inst.operands[0].reg << 12;
inst.instruction |= inst.operands[1].reg << 8;
encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
-
}
static void
opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
break;
default:
- abort();
+ abort ();
}
inst.instruction = opcode;
constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
_("'CPSR' or 'SPSR' expected"));
}
-
+
inst.instruction |= inst.operands[0].reg << 8;
inst.instruction |= (flags & SPSR_BIT) >> 2;
inst.instruction |= inst.operands[1].imm & 0xff;
do_t_push_pop (void)
{
unsigned mask;
-
+
constraint (inst.operands[0].writeback,
_("push/pop do not support {reglist}^"));
constraint (inst.reloc.type != BFD_RELOC_UNUSED,
else if (unified_syntax)
{
inst.instruction = THUMB_OP32 (inst.instruction);
- encode_thumb2_ldmstm(13, mask, TRUE);
+ encode_thumb2_ldmstm (13, mask, TRUE);
}
else
{
case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
default: abort ();
}
-
+
inst.instruction |= inst.operands[0].reg;
inst.instruction |= inst.operands[2].reg << 3;
}
case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
default: abort ();
}
-
+
inst.instruction |= inst.operands[0].reg;
inst.instruction |= inst.operands[2].reg << 3;
}
}
/* Neon instruction encoder helpers. */
-
+
/* Encodings for the different types for various Neon opcodes. */
/* An "invalid" code for the following tables. */
unsigned float_or_poly;
unsigned scalar_or_imm;
};
-
+
/* Map overloaded Neon opcodes to their respective encodings. */
#define NEON_ENC_TAB \
X(vabd, 0x0000700, 0x1200d00, N_INV), \
S - Scalar
R - ARM register
L - D<n> register list
-
+
This table is used to generate various data:
- enumerations of the form NS_DDR to be used as arguments to
neon_select_shape.
- a table classifying shapes into single, double, quad, mixed.
- - a table used to drive neon_select_shape.
-*/
+ - a table used to drive neon_select_shape. */
#define NEON_SHAPE_DEF \
X(3, (D, D, D), DOUBLE), \
inst.operands[1] = inst.operands[0];
va_start (ap, shape);
-
+
for (; shape != NS_NULL; shape = va_arg (ap, int))
{
unsigned j;
if (matches)
break;
}
-
+
va_end (ap);
if (shape == NS_NULL && first_shape != NS_NULL)
*g_type = NT_untyped;
}
}
-
+
/* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
operand type, i.e. the single type specified in a Neon instruction when it
is the only one given. */
neon_type_promote (struct neon_type_el *key, unsigned thisarg)
{
struct neon_type_el dest = *key;
-
+
assert ((thisarg & N_EQK) != 0);
-
+
neon_modify_type_size (thisarg, &dest.type, &dest.size);
return dest;
default: ;
}
-
+
return N_UTYP;
}
*type = NT_float;
else
return FAIL;
-
+
return SUCCESS;
}
enum neon_el_type type;
unsigned destmask;
int i;
-
+
destmask = 0;
-
+
for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
{
if (el_type_of_type_chk (&type, &size, allowed & i) == SUCCESS)
destmask |= type_chk_of_el_type (type, size);
}
}
-
+
return destmask;
}
return badtype;
}
}
-
+
if ((thisarg & N_EQK) == 0)
{
unsigned given_type = type_chk_of_el_type (g_type, g_size);
do_vfp_nsyn_opcode (const char *opname)
{
const struct asm_opcode *opcode;
-
+
opcode = hash_find (arm_ops_hsh, opname);
if (!opcode)
et = neon_check_type (2, rs,
N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
break;
-
+
case 3:
rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
et = neon_check_type (3, rs,
do_vfp_nsyn_mla_mls (enum neon_shape rs)
{
int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
-
+
if (rs == NS_FFF)
{
if (is_mla)
{
enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
-
+
if (rs == NS_FF)
do_vfp_nsyn_opcode ("fsqrts");
else
enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
N_F32 | N_F64 | N_KEY | N_VFP);
-
+
if (rs == NS_FFF)
do_vfp_nsyn_opcode ("fdivs");
else
enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
N_F32 | N_F64 | N_KEY | N_VFP);
-
+
if (rs == NS_FFF)
{
inst.instruction = NEON_ENC_SINGLE (inst.instruction);
{
enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
-
+
if (rs == NS_FF)
{
inst.instruction = NEON_ENC_SINGLE (inst.instruction);
default:
abort ();
}
-
+
if (rs == NS_FI)
{
inst.instruction = NEON_ENC_SINGLE (inst.instruction);
/* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
if (i & (1 << 24))
i |= 1 << 28;
-
+
i &= ~(1 << 24);
-
+
i |= 0xef000000;
}
else
i |= 0xf2000000;
-
+
return i;
}
|28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
| U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
-
+
SIZE is passed in bits. -1 means size field isn't changed, in case it has a
different meaning for some instruction. */
inst.instruction |= (ubit != 0) << 24;
if (size != -1)
inst.instruction |= neon_logbits (size) << 20;
-
+
inst.instruction = neon_dp_fixup (inst.instruction);
}
the instruction. *OP is passed as the initial value of the op field, and
may be set to a different value depending on the constant (i.e.
"MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
- MVN). If the immediate looks like a repeated parttern then also
+ MVN). If the immediate looks like a repeated pattern then also
try smaller element sizes. */
static int
enum neon_opc opcode = inst.instruction & 0x0fffffff;
unsigned immbits;
int cmode;
-
+
if (et.type == NT_invtype)
return;
-
+
inst.instruction = NEON_ENC_IMMED (inst.instruction);
immbits = inst.operands[1].imm;
case N_MNEM_vbic:
cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
break;
-
+
case N_MNEM_vorr:
cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
break;
-
+
case N_MNEM_vand:
/* Pseudo-instruction for VBIC. */
neon_invert_size (&immbits, 0, et.size);
cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
break;
-
+
case N_MNEM_vorn:
/* Pseudo-instruction for VORR. */
neon_invert_size (&immbits, 0, et.size);
cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
break;
-
+
default:
abort ();
}
inst.instruction |= HI1 (inst.operands[0].reg) << 22;
inst.instruction |= cmode << 8;
neon_write_immbits (immbits);
-
+
inst.instruction = neon_dp_fixup (inst.instruction);
}
}
if (inst.uncond_value != -1)
inst.instruction |= inst.uncond_value << 28;
}
-
+
if ((check & NEON_CHECK_ARCH)
&& !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
{
first_error (_(BAD_FPU));
return FAIL;
}
-
+
return SUCCESS;
}
inst.instruction |= neon_quad (rs) << 6;
inst.instruction |= (et.type == NT_float) << 10;
inst.instruction |= neon_logbits (et.size) << 18;
-
+
inst.instruction = neon_dp_fixup (inst.instruction);
}
}
if (regno > 7 || elno > 3)
goto bad_scalar;
return regno | (elno << 3);
-
+
case 32:
if (regno > 15 || elno > 1)
goto bad_scalar;
/* Give a more helpful error message if we have an invalid type. */
if (et.type == NT_invtype)
return;
-
+
scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
inst.instruction |= HI1 (inst.operands[0].reg) << 22;
{
enum neon_shape rs;
struct neon_type_el et;
-
+
if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
return;
rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY);
-
+
inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
inst.instruction |= HI1 (inst.operands[0].reg) << 22;
inst.instruction |= LOW4 (inst.operands[1].reg);
inst.instruction |= neon_quad (rs) << 6;
inst.instruction |= (et.type == NT_float) << 10;
inst.instruction |= neon_logbits (et.size) << 18;
-
+
inst.instruction = neon_dp_fixup (inst.instruction);
}
/* This gets the bounds check, size encoding and immediate bits calculation
right. */
et.size /= 2;
-
+
/* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
VQMOVN.I<size> <Dd>, <Qm>. */
if (imm == 0)
do_neon_qmovn ();
return;
}
-
+
constraint (imm < 1 || (unsigned)imm > et.size,
_("immediate out of range"));
neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
/* This gets the bounds check, size encoding and immediate bits calculation
right. */
et.size /= 2;
-
+
/* If immediate is zero then we are a pseudo-instruction for
VMOVN.I<size> <Dd>, <Qm> */
if (imm == 0)
do_neon_movn ();
return;
}
-
+
constraint (imm < 1 || (unsigned)imm > et.size,
_("immediate out of range for narrowing operation"));
neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
inst.instruction |= LOW4 (inst.operands[1].reg);
inst.instruction |= HI1 (inst.operands[1].reg) << 5;
inst.instruction |= neon_logbits (et.size) << 18;
-
+
inst.instruction = neon_dp_fixup (inst.instruction);
}
else
"source" and "destination" registers must have the same width. Hack that
here by making the size equal to the key (wider, in this case) operand. */
unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
-
+
CVT_VAR (0, N_S32, N_F32);
CVT_VAR (1, N_U32, N_F32);
CVT_VAR (2, N_F32, N_S32);
CVT_VAR (3, N_F32, N_U32);
-
+
whole_reg = N_VFP;
-
+
/* VFP instructions. */
CVT_VAR (4, N_F32, N_F64);
CVT_VAR (5, N_F64, N_F32);
CVT_VAR (15, N_U16, N_F32 | key);
CVT_VAR (16, N_S16, N_F64 | key);
CVT_VAR (17, N_U16, N_F64 | key);
-
+
return -1;
#undef CVT_VAR
}
do_vfp_nsyn_cvt (enum neon_shape rs, int flavour)
{
const char *opname = 0;
-
+
if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI)
{
/* Conversions with immediate bitshift. */
if (inst.operands[1].isreg)
{
enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
-
+
inst.instruction = NEON_ENC_INTEGER (inst.instruction);
inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
inst.instruction |= HI1 (inst.operands[0].reg) << 22;
/* Encode instructions of form:
|28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
- | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm |
-
-*/
+ | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
static void
neon_mixed_length (struct neon_type_el et, unsigned size)
inst.instruction |= HI1 (inst.operands[2].reg) << 5;
inst.instruction |= (et.type == NT_unsigned) << 24;
inst.instruction |= neon_logbits (size) << 20;
-
+
inst.instruction = neon_dp_fixup (inst.instruction);
}
inst.instruction |= HI1 (inst.operands[2].reg) << 5;
inst.instruction |= neon_quad (rs) << 6;
inst.instruction |= imm << 8;
-
+
inst.instruction = neon_dp_fixup (inst.instruction);
}
inst.instruction |= neon_quad (rs) << 6;
inst.instruction |= x << 17;
inst.instruction |= sizebits << 16;
-
+
inst.instruction = neon_dp_fixup (inst.instruction);
}
else
(Two ARM regs to two VFP singles.)
15. VMOV <Sd>, <Se>, <Rn>, <Rm>
(Two VFP singles to two ARM regs.)
-
+
These cases can be disambiguated using neon_select_shape, except cases 1/9
and 3/11 which depend on the operand type too.
-
+
All the encoded bits are hardcoded by this function.
-
+
Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
Cases 5, 7 may be used with VFPv2 and above.
-
+
FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
- can specify a type where it doesn't make sense to, and is ignored).
-*/
+ can specify a type where it doesn't make sense to, and is ignored). */
static void
do_neon_mov (void)
inst.instruction = neon_dp_fixup (inst.instruction);
}
break;
-
+
case NS_DI: /* case 3/11. */
et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
inst.error = NULL;
neon_move_immediate ();
inst.instruction = neon_dp_fixup (inst.instruction);
break;
-
+
case NS_SR: /* case 4. */
{
unsigned bcdebits = 0;
inst.instruction |= (bcdebits >> 2) << 21;
}
break;
-
+
case NS_DRR: /* case 5 (fmdrr). */
constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
_(BAD_FPU));
inst.instruction |= inst.operands[1].reg << 12;
inst.instruction |= inst.operands[2].reg << 16;
break;
-
+
case NS_RS: /* case 6. */
{
struct neon_type_el et = neon_check_type (2, NS_NULL,
inst.instruction |= (abcdebits >> 2) << 21;
}
break;
-
+
case NS_RRD: /* case 7 (fmrrd). */
constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
_(BAD_FPU));
inst.instruction |= LOW4 (inst.operands[2].reg);
inst.instruction |= HI1 (inst.operands[2].reg) << 5;
break;
-
+
case NS_FF: /* case 8 (fcpys). */
do_vfp_nsyn_opcode ("fcpys");
break;
-
+
case NS_FI: /* case 10 (fconsts). */
ldconst = "fconsts";
encode_fconstd:
else
first_error (_("immediate out of range"));
break;
-
+
case NS_RF: /* case 12 (fmrs). */
do_vfp_nsyn_opcode ("fmrs");
break;
-
+
case NS_FR: /* case 13 (fmsr). */
do_vfp_nsyn_opcode ("fmsr");
break;
-
+
/* The encoders for the fmrrs and fmsrr instructions expect three operands
(one of which is a list), but we have parsed four. Do some fiddling to
make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
do_vfp_nsyn_opcode ("fmrrs");
break;
-
+
case NS_FFRR: /* case 15 (fmsrr). */
constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
_("VFP registers must be adjacent"));
memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
do_vfp_nsyn_opcode ("fmsrr");
break;
-
+
default:
abort ();
}
{
unsigned listlenbits;
neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
-
+
if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
{
first_error (_("bad list length for table lookup"));
return;
}
-
+
listlenbits = inst.operands[1].imm - 1;
inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
inst.instruction |= HI1 (inst.operands[0].reg) << 22;
inst.instruction |= LOW4 (inst.operands[2].reg);
inst.instruction |= HI1 (inst.operands[2].reg) << 5;
inst.instruction |= listlenbits << 8;
-
+
inst.instruction = neon_dp_fixup (inst.instruction);
}
inst.instruction |= HI1 (inst.operands[1].reg) << 22;
inst.instruction |= offsetbits;
-
+
do_vfp_cond_or_thumb ();
}
do_neon_ldr_str (void)
{
int is_ldr = (inst.instruction & (1 << 20)) != 0;
-
+
if (inst.operands[0].issingle)
{
if (is_ldr)
| (((inst.instruction >> 8) & 3) << 3);
typebits = typetable[idx];
-
+
constraint (typebits == -1, _("bad list type for instruction"));
inst.instruction &= ~0xf00;
{
va_list ap;
int result = FAIL, thissize, thisalign;
-
+
if (!inst.operands[1].immisalign)
{
*do_align = 0;
return SUCCESS;
}
-
+
va_start (ap, do_align);
do
*do_align = 1;
else
first_error (_("unsupported alignment for instruction"));
-
+
return result;
}
int align = inst.operands[1].imm >> 8;
int n = (inst.instruction >> 8) & 3;
int max_el = 64 / et.size;
-
+
if (et.type == NT_invtype)
return;
-
+
constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
_("bad list length"));
constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
&& et.size == 8,
_("stride of 2 unavailable when element size is 8"));
-
+
switch (n)
{
case 0: /* VLD1 / VST1. */
/* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
inst.instruction |= 1 << (4 + logsize);
-
+
inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
inst.instruction |= logsize << 10;
}
inst.instruction = NEON_ENC_INTERLV (inst.instruction);
do_neon_ld_st_interleave ();
break;
-
+
case NEON_ALL_LANES:
inst.instruction = NEON_ENC_DUP (inst.instruction);
do_neon_ld_dup ();
break;
-
+
default:
inst.instruction = NEON_ENC_LANE (inst.instruction);
do_neon_ld_st_lane ();
inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
inst.instruction |= HI1 (inst.operands[0].reg) << 22;
inst.instruction |= inst.operands[1].reg << 16;
-
+
if (inst.operands[1].postind)
{
int postreg = inst.operands[1].imm & 0xf;
inst.instruction |= 0xd;
}
else
- inst.instruction |= 0xf;
-
+ inst.instruction |= 0xf;
+
if (thumb_mode)
inst.instruction |= 0xf9000000;
else
inst.instruction |= 0xf4000000;
}
-
\f
/* Overall per-instruction processing. */
as_bad ("%s -- `%s'", inst.error, str);
return;
}
- if (inst.relax) {
- output_relax_insn();
+ if (inst.relax)
+ {
+ output_relax_insn ();
return;
- }
+ }
if (inst.size == 0)
return;
const struct asm_cond *cond;
char save[2];
bfd_boolean neon_supported;
-
+
neon_supported = ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1);
/* Scan up to the end of the mnemonic, which must end in white space,
if (end[0] == '.')
{
int offset = 2;
-
+
/* The .w and .n suffixes are only valid if the unified syntax is in
use. */
if (unified_syntax && end[1] == 'w')
*str = end + offset;
- if (end[offset] == '.')
+ if (end[offset] == '.')
{
/* See if we have a Neon type suffix (possible in either unified or
non-unified ARM syntax mode). */
ARM_SET_INTERWORK (sym, support_interwork);
#endif
- /* Note - do not allow local symbols (.Lxxx) to be labeled
+ /* Note - do not allow local symbols (.Lxxx) to be labelled
as Thumb functions. This is because these labels, whilst
they exist inside Thumb code, are not the entry points for
possible ARM->Thumb calls. Also, these labels can be used
buf = fragp->fr_literal + fragp->fr_fix;
old_op = bfd_get_16(abfd, buf);
- if (fragp->fr_symbol) {
+ if (fragp->fr_symbol)
+ {
exp.X_op = O_symbol;
exp.X_add_symbol = fragp->fr_symbol;
- } else {
+ }
+ else
+ {
exp.X_op = O_constant;
- }
+ }
exp.X_add_number = fragp->fr_offset;
opcode = fragp->fr_subtype;
switch (opcode)
case T_MNEM_strh:
if (fragp->fr_var == 4)
{
- insn = THUMB_OP32(opcode);
+ insn = THUMB_OP32 (opcode);
if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
{
insn |= (old_op & 0x700) << 4;
pc_rel = 0;
break;
default:
- abort();
+ abort ();
}
fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
reloc_type);
/* Get the address of a symbol during relaxation. */
static addressT
-relaxed_symbol_addr(fragS *fragp, long stretch)
+relaxed_symbol_addr (fragS *fragp, long stretch)
{
fragS *sym_frag;
addressT addr;
offsetT val;
/* Assume worst case for symbols not known to be in the same section. */
- if (!S_IS_DEFINED(fragp->fr_symbol)
+ if (!S_IS_DEFINED (fragp->fr_symbol)
|| sec != S_GET_SEGMENT (fragp->fr_symbol))
return 4;
- val = relaxed_symbol_addr(fragp, stretch);
+ val = relaxed_symbol_addr (fragp, stretch);
addr = fragp->fr_address + fragp->fr_fix;
addr = (addr + 4) & ~3;
/* Force misaligned targets to 32-bit variant. */
offsetT limit;
/* Assume worst case for symbols not known to be in the same section. */
- if (!S_IS_DEFINED(fragp->fr_symbol)
+ if (!S_IS_DEFINED (fragp->fr_symbol)
|| sec != S_GET_SEGMENT (fragp->fr_symbol))
return 4;
- val = relaxed_symbol_addr(fragp, stretch);
+ val = relaxed_symbol_addr (fragp, stretch);
addr = fragp->fr_address + fragp->fr_fix + 4;
val -= addr;
switch (fragp->fr_subtype)
{
case T_MNEM_ldr_pc2:
- newsize = relax_adr(fragp, sec, stretch);
+ newsize = relax_adr (fragp, sec, stretch);
break;
case T_MNEM_ldr_pc:
case T_MNEM_ldr_sp:
case T_MNEM_str_sp:
- newsize = relax_immediate(fragp, 8, 2);
+ newsize = relax_immediate (fragp, 8, 2);
break;
case T_MNEM_ldr:
case T_MNEM_str:
- newsize = relax_immediate(fragp, 5, 2);
+ newsize = relax_immediate (fragp, 5, 2);
break;
case T_MNEM_ldrh:
case T_MNEM_strh:
- newsize = relax_immediate(fragp, 5, 1);
+ newsize = relax_immediate (fragp, 5, 1);
break;
case T_MNEM_ldrb:
case T_MNEM_strb:
- newsize = relax_immediate(fragp, 5, 0);
+ newsize = relax_immediate (fragp, 5, 0);
break;
case T_MNEM_adr:
- newsize = relax_adr(fragp, sec, stretch);
+ newsize = relax_adr (fragp, sec, stretch);
break;
case T_MNEM_mov:
case T_MNEM_movs:
case T_MNEM_cmp:
case T_MNEM_cmn:
- newsize = relax_immediate(fragp, 8, 0);
+ newsize = relax_immediate (fragp, 8, 0);
break;
case T_MNEM_b:
- newsize = relax_branch(fragp, sec, 11, stretch);
+ newsize = relax_branch (fragp, sec, 11, stretch);
break;
case T_MNEM_bcond:
- newsize = relax_branch(fragp, sec, 8, stretch);
+ newsize = relax_branch (fragp, sec, 8, stretch);
break;
case T_MNEM_add_sp:
case T_MNEM_add_pc:
newsize = relax_addsub (fragp, sec);
break;
default:
- abort();
+ abort ();
}
fragp->fr_var = newsize;
/* Freeze wide instructions that are at or before the same location as
in the previous pass. This avoids infinite loops.
- Don't freeze them unconditionally because targets may be artificialy
- misaligned by the expansion of preceeding frags. */
+ Don't freeze them unconditionally because targets may be artificially
+ misaligned by the expansion of preceding frags. */
if (stretch <= 0 && newsize > 2)
{
md_convert_frag (sec->owner, sec, fragp);
- frag_wane(fragp);
+ frag_wane (fragp);
}
return newsize - oldsize;
static void add_unwind_adjustsp (offsetT);
-/* Cenerate and deferred unwind frame offset. */
+/* Generate any deferred unwind frame offset. */
static void
flush_pending_unwind (void)
obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
- /* Set the setion link for index tables. */
+ /* Set the section link for index tables. */
if (idx)
elf_linked_to_section (now_seg) = text_seg;
}
if (unwind.personality_index == -2)
{
if (have_data)
- as_bad (_("handerdata in cantunwind frame"));
+ as_bad (_("handlerdata in cantunwind frame"));
return 1; /* EXIDX_CANTUNWIND. */
}
will need. Otherwise we want to use the calculated base.
For WinCE we skip the bias for externals as well, since this
is how the MS ARM-CE assembler behaves and we want to be compatible. */
- if (fixP->fx_pcrel
+ if (fixP->fx_pcrel
&& ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
|| (arm_force_relocation (fixP)
#ifdef TE_WINCE
case BFD_RELOC_ARM_PCREL_BLX:
case BFD_RELOC_ARM_PLT32:
#ifdef TE_WINCE
- /* When handling fixups immediately, because we have already
+ /* When handling fixups immediately, because we have already
discovered the value of a symbol, or the address of the frag involved
we must account for the offset by +8, as the OS loader will never see the reloc.
see fixup_segment() in write.c
fixP->fx_done = 1;
/* On a 64-bit host, silently truncate 'value' to 32 bits for
- consistency with the behavior on 32-bit hosts. Remember value
+ consistency with the behaviour on 32-bit hosts. Remember value
for emit_reloc. */
value &= 0xffffffff;
value ^= 0x80000000;
- value -= 0x80000000;
+ value -= 0x80000000;
*valP = value;
fixP->fx_addnumber = value;
instruction. */
insn &= 0xfffff000;
insn |= encoded_addend;
-
- /* Update the instruction. */
+
+ /* Update the instruction. */
md_number_to_chars (buf, insn, INSN_SIZE);
}
break;
of the instruction. */
insn &= 0xfffff000;
insn |= addend_abs;
-
- /* Update the instruction. */
+
+ /* Update the instruction. */
md_number_to_chars (buf, insn, INSN_SIZE);
}
break;
four into bits 8 .. 11. */
insn &= 0xfffff0f0;
insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
-
- /* Update the instruction. */
+
+ /* Update the instruction. */
md_number_to_chars (buf, insn, INSN_SIZE);
}
break;
bits of the instruction. */
insn &= 0xfffffff0;
insn |= addend_abs >> 2;
-
- /* Update the instruction. */
+
+ /* Update the instruction. */
md_number_to_chars (buf, insn, INSN_SIZE);
}
break;
for (pool = list_of_pools; pool; pool = pool->next)
{
- /* Put it at the end of the relevent section. */
+ /* Put it at the end of the relevant section. */
subseg_set (pool->section, pool->sub_section);
#ifdef OBJ_ELF
arm_elf_change_section ();
if (opt->name == NULL)
{
- as_bad (_("unknown architectural extnsion `%s'"), str);
+ as_bad (_("unknown architectural extension `%s'"), str);
return 0;
}
mcpu_cpu_opt = &opt->value;
mcpu_fpu_opt = &opt->default_fpu;
if (opt->canonical_name)
- strcpy(selected_cpu_name, opt->canonical_name);
+ strcpy (selected_cpu_name, opt->canonical_name);
else
{
int i;
{
march_cpu_opt = &opt->value;
march_fpu_opt = &opt->default_fpu;
- strcpy(selected_cpu_name, opt->name);
+ strcpy (selected_cpu_name, opt->name);
if (ext != NULL)
return arm_parse_extension (ext, &march_cpu_opt);
char *p;
p = selected_cpu_name;
- if (strncmp(p, "armv", 4) == 0)
+ if (strncmp (p, "armv", 4) == 0)
{
int i;
-
+
p += 4;
for (i = 0; p[i]; i++)
p[i] = TOUPPER (p[i]);
char saved_char;
name = input_line_pointer;
- while (*input_line_pointer && !ISSPACE(*input_line_pointer))
+ while (*input_line_pointer && !ISSPACE (*input_line_pointer))
input_line_pointer++;
saved_char = *input_line_pointer;
*input_line_pointer = 0;
mcpu_cpu_opt = &opt->value;
selected_cpu = opt->value;
if (opt->canonical_name)
- strcpy(selected_cpu_name, opt->canonical_name);
+ strcpy (selected_cpu_name, opt->canonical_name);
else
{
int i;
char *name;
name = input_line_pointer;
- while (*input_line_pointer && !ISSPACE(*input_line_pointer))
+ while (*input_line_pointer && !ISSPACE (*input_line_pointer))
input_line_pointer++;
saved_char = *input_line_pointer;
*input_line_pointer = 0;
{
mcpu_cpu_opt = &opt->value;
selected_cpu = opt->value;
- strcpy(selected_cpu_name, opt->name);
+ strcpy (selected_cpu_name, opt->name);
ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
*input_line_pointer = saved_char;
demand_empty_rest_of_line ();
char *name;
name = input_line_pointer;
- while (*input_line_pointer && !ISSPACE(*input_line_pointer))
+ while (*input_line_pointer && !ISSPACE (*input_line_pointer))
input_line_pointer++;
saved_char = *input_line_pointer;
*input_line_pointer = 0;
char *name;
name = input_line_pointer;
- while (*input_line_pointer && !ISSPACE(*input_line_pointer))
+ while (*input_line_pointer && !ISSPACE (*input_line_pointer))
input_line_pointer++;
saved_char = *input_line_pointer;
*input_line_pointer = 0;
-
+
for (opt = arm_fpus; opt->name != NULL; opt++)
if (streq (opt->name, name))
{
msgstr ""
"Project-Id-Version: PACKAGE VERSION\n"
"Report-Msgid-Bugs-To: bug-binutils@gnu.org\n"
-"POT-Creation-Date: 2007-10-18 11:59+0100\n"
+"POT-Creation-Date: 2007-10-18 12:49+0100\n"
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
"Language-Team: LANGUAGE <LL@li.org>\n"
msgstr ""
#. We can't actually support subtracting a symbol.
-#: cgen.c:884 config/tc-arc.c:1247 config/tc-arm.c:1524 config/tc-arm.c:8153
-#: config/tc-arm.c:8204 config/tc-arm.c:8437 config/tc-arm.c:9160
-#: config/tc-arm.c:9964 config/tc-arm.c:9992 config/tc-arm.c:10249
-#: config/tc-arm.c:10266 config/tc-arm.c:10388 config/tc-avr.c:1022
+#: cgen.c:884 config/tc-arc.c:1247 config/tc-arm.c:1521 config/tc-arm.c:8147
+#: config/tc-arm.c:8198 config/tc-arm.c:8431 config/tc-arm.c:9154
+#: config/tc-arm.c:9957 config/tc-arm.c:9985 config/tc-arm.c:10242
+#: config/tc-arm.c:10259 config/tc-arm.c:10381 config/tc-avr.c:1022
#: config/tc-cris.c:3984 config/tc-d10v.c:1502 config/tc-d30v.c:1903
#: config/tc-mips.c:4184 config/tc-mips.c:5308 config/tc-mips.c:6247
#: config/tc-mips.c:6839 config/tc-msp430.c:1937 config/tc-ppc.c:5579
msgid "cannot create floating-point number"
msgstr ""
-#: config/atof-ieee.c:784 config/atof-vax.c:450 config/tc-arm.c:919
+#: config/atof-ieee.c:784 config/atof-vax.c:450 config/tc-arm.c:917
#: config/tc-ia64.c:11721 config/tc-tic30.c:1261 config/tc-tic4x.c:2706
msgid "Unrecognized or unsupported floating point constant"
msgstr ""
msgid "internal error: can't hash macro `%s': %s"
msgstr ""
-#: config/tc-alpha.c:4998 config/tc-arm.c:6061 config/tc-arm.c:6073
+#: config/tc-alpha.c:4998 config/tc-arm.c:6057 config/tc-arm.c:6069
#: config/tc-i960.c:708 config/tc-xtensa.c:5177 config/tc-xtensa.c:5255
#: config/tc-xtensa.c:5301 config/tc-z80.c:1893
msgid "syntax error"
msgid "could not set architecture and machine"
msgstr ""
-#: config/tc-arc.c:212 config/tc-arm.c:19536 config/tc-score.c:6522
+#: config/tc-arc.c:212 config/tc-arm.c:19528 config/tc-score.c:6522
#: config/tc-score.c:6538 config/tc-score.c:6543
msgid "virtual memory exhausted"
msgstr ""
msgid "conditional branch follows set of flags"
msgstr ""
-#: config/tc-arc.c:1890 config/tc-arm.c:14179
+#: config/tc-arc.c:1890 config/tc-arm.c:14168
#, c-format
msgid "bad instruction `%s'"
msgstr ""
msgid "iWMMXt data register expected"
msgstr ""
-#: config/tc-arm.c:501 config/tc-arm.c:5870
+#: config/tc-arm.c:501 config/tc-arm.c:5866
msgid "iWMMXt control register expected"
msgstr ""
msgid "selected FPU does not support instruction"
msgstr ""
-#: config/tc-arm.c:803
+#: config/tc-arm.c:801
msgid "immediate expression requires a # prefix"
msgstr ""
-#: config/tc-arm.c:830 config/tc-score.c:5605 expr.c:1300 read.c:2439
+#: config/tc-arm.c:828 config/tc-score.c:5605 expr.c:1300 read.c:2439
msgid "bad expression"
msgstr ""
-#: config/tc-arm.c:841 config/tc-i860.c:1003 config/tc-sparc.c:2898
+#: config/tc-arm.c:839 config/tc-i860.c:1003 config/tc-sparc.c:2898
msgid "bad segment"
msgstr ""
-#: config/tc-arm.c:858 config/tc-arm.c:4395 config/tc-i960.c:1300
+#: config/tc-arm.c:856 config/tc-arm.c:4392 config/tc-i960.c:1300
#: config/tc-score.c:980
msgid "invalid constant"
msgstr ""
-#: config/tc-arm.c:988
+#: config/tc-arm.c:986
msgid "expected #constant"
msgstr ""
-#: config/tc-arm.c:1149
+#: config/tc-arm.c:1147
#, c-format
msgid "unexpected character `%c' in type specifier"
msgstr ""
-#: config/tc-arm.c:1166
+#: config/tc-arm.c:1164
#, c-format
msgid "bad size %d in type specifier"
msgstr ""
-#: config/tc-arm.c:1216
+#: config/tc-arm.c:1214
msgid "only one type should be specified for operand"
msgstr ""
-#: config/tc-arm.c:1222
+#: config/tc-arm.c:1220
msgid "vector type expected"
msgstr ""
-#: config/tc-arm.c:1294
+#: config/tc-arm.c:1292
msgid "can't redefine type for operand"
msgstr ""
-#: config/tc-arm.c:1305
+#: config/tc-arm.c:1303
msgid "only D registers may be indexed"
msgstr ""
-#: config/tc-arm.c:1311
+#: config/tc-arm.c:1309
msgid "can't change index for operand"
msgstr ""
-#: config/tc-arm.c:1327 config/tc-arm.c:3996
+#: config/tc-arm.c:1325 config/tc-arm.c:3993
msgid "constant expression required"
msgstr ""
-#: config/tc-arm.c:1371
+#: config/tc-arm.c:1368
msgid "register operand expected, but got scalar"
msgstr ""
-#: config/tc-arm.c:1404
+#: config/tc-arm.c:1401
msgid "scalar must have an index"
msgstr ""
-#: config/tc-arm.c:1409 config/tc-arm.c:13146 config/tc-arm.c:13194
-#: config/tc-arm.c:13596
+#: config/tc-arm.c:1406 config/tc-arm.c:13135 config/tc-arm.c:13183
+#: config/tc-arm.c:13585
msgid "scalar index out of range"
msgstr ""
-#: config/tc-arm.c:1456
+#: config/tc-arm.c:1453
msgid "bad range in register list"
msgstr ""
-#: config/tc-arm.c:1464 config/tc-arm.c:1473 config/tc-arm.c:1514
+#: config/tc-arm.c:1461 config/tc-arm.c:1470 config/tc-arm.c:1511
#, c-format
msgid "Warning: duplicated register (r%d) in register list"
msgstr ""
-#: config/tc-arm.c:1476
+#: config/tc-arm.c:1473
msgid "Warning: register range not in ascending order"
msgstr ""
-#: config/tc-arm.c:1487
+#: config/tc-arm.c:1484
msgid "missing `}'"
msgstr ""
-#: config/tc-arm.c:1503
+#: config/tc-arm.c:1500
msgid "invalid register mask"
msgstr ""
-#: config/tc-arm.c:1585
+#: config/tc-arm.c:1582
msgid "expecting {"
msgstr ""
-#: config/tc-arm.c:1640 config/tc-arm.c:1684
+#: config/tc-arm.c:1637 config/tc-arm.c:1681
msgid "register out of range in list"
msgstr ""
-#: config/tc-arm.c:1656 config/tc-arm.c:1701 config/tc-h8300.c:989
+#: config/tc-arm.c:1653 config/tc-arm.c:1698 config/tc-h8300.c:989
#: config/tc-mips.c:10188 config/tc-mips.c:10210
msgid "invalid register list"
msgstr ""
-#: config/tc-arm.c:1662 config/tc-arm.c:3461 config/tc-arm.c:3594
+#: config/tc-arm.c:1659 config/tc-arm.c:3458 config/tc-arm.c:3591
msgid "register list not in ascending order"
msgstr ""
-#: config/tc-arm.c:1693
+#: config/tc-arm.c:1690
msgid "register range not in ascending order"
msgstr ""
-#: config/tc-arm.c:1726
+#: config/tc-arm.c:1723
msgid "non-contiguous register range"
msgstr ""
-#: config/tc-arm.c:1852
+#: config/tc-arm.c:1849
msgid "don't use Rn-Rm syntax with non-unit stride"
msgstr ""
-#: config/tc-arm.c:1907
+#: config/tc-arm.c:1904
msgid "error parsing element/structure list"
msgstr ""
-#: config/tc-arm.c:1913
+#: config/tc-arm.c:1910
msgid "expected }"
msgstr ""
-#: config/tc-arm.c:1969
+#: config/tc-arm.c:1966
#, c-format
msgid "ignoring attempt to redefine built-in register '%s'"
msgstr ""
-#: config/tc-arm.c:1974
+#: config/tc-arm.c:1971
#, c-format
msgid "ignoring redefinition of register alias '%s'"
msgstr ""
-#: config/tc-arm.c:2002
+#: config/tc-arm.c:1999
msgid "attempt to redefine typed alias"
msgstr ""
-#: config/tc-arm.c:2040
+#: config/tc-arm.c:2037
#, c-format
msgid "unknown register '%s' -- .req ignored"
msgstr ""
-#: config/tc-arm.c:2136
+#: config/tc-arm.c:2132
msgid "bad type for register"
msgstr ""
-#: config/tc-arm.c:2147
+#: config/tc-arm.c:2143
msgid "expression must be constant"
msgstr ""
-#: config/tc-arm.c:2164
+#: config/tc-arm.c:2160
msgid "can't redefine the type of a register alias"
msgstr ""
-#: config/tc-arm.c:2171
+#: config/tc-arm.c:2167
msgid "you must specify a single type only"
msgstr ""
-#: config/tc-arm.c:2184
+#: config/tc-arm.c:2180
msgid "can't redefine the index of a scalar alias"
msgstr ""
-#: config/tc-arm.c:2192
+#: config/tc-arm.c:2188
msgid "scalar index must be constant"
msgstr ""
-#: config/tc-arm.c:2201
+#: config/tc-arm.c:2197
msgid "expecting ]"
msgstr ""
-#: config/tc-arm.c:2238
+#: config/tc-arm.c:2234
msgid "invalid syntax for .req directive"
msgstr ""
-#: config/tc-arm.c:2244
+#: config/tc-arm.c:2240
msgid "invalid syntax for .dn directive"
msgstr ""
-#: config/tc-arm.c:2250
+#: config/tc-arm.c:2246
msgid "invalid syntax for .qn directive"
msgstr ""
-#: config/tc-arm.c:2276
+#: config/tc-arm.c:2272
msgid "invalid syntax for .unreq directive"
msgstr ""
-#: config/tc-arm.c:2282
+#: config/tc-arm.c:2278
#, c-format
msgid "unknown register alias '%s'"
msgstr ""
-#: config/tc-arm.c:2284
+#: config/tc-arm.c:2280
#, c-format
msgid "ignoring attempt to undefine built-in register '%s'"
msgstr ""
-#: config/tc-arm.c:2435
+#: config/tc-arm.c:2431
#, c-format
msgid "Failed to find real start of function: %s\n"
msgstr ""
-#: config/tc-arm.c:2451
+#: config/tc-arm.c:2447
msgid "selected processor does not support THUMB opcodes"
msgstr ""
-#: config/tc-arm.c:2465
+#: config/tc-arm.c:2461
msgid "selected processor does not support ARM opcodes"
msgstr ""
-#: config/tc-arm.c:2478
+#: config/tc-arm.c:2474
#, c-format
msgid "invalid instruction size selected (%d)"
msgstr ""
-#: config/tc-arm.c:2510
+#: config/tc-arm.c:2506
#, c-format
msgid "invalid operand to .code directive (%d) (expecting 16 or 32)"
msgstr ""
-#: config/tc-arm.c:2566
+#: config/tc-arm.c:2562
#, c-format
msgid "expected comma after name \"%s\""
msgstr ""
-#: config/tc-arm.c:2616 config/tc-m32r.c:588
+#: config/tc-arm.c:2612 config/tc-m32r.c:588
#, c-format
msgid "symbol `%s' already defined"
msgstr ""
-#: config/tc-arm.c:2650
+#: config/tc-arm.c:2646
#, c-format
msgid "unrecognized syntax mode \"%s\""
msgstr ""
-#: config/tc-arm.c:2671
+#: config/tc-arm.c:2667
#, c-format
msgid "alignment too large: %d assumed"
msgstr ""
-#: config/tc-arm.c:2674
+#: config/tc-arm.c:2670
msgid "alignment negative. 0 assumed."
msgstr ""
-#: config/tc-arm.c:2821
+#: config/tc-arm.c:2817
msgid "literal pool overflow"
msgstr ""
-#: config/tc-arm.c:2977 config/tc-arm.c:5805
+#: config/tc-arm.c:2973 config/tc-arm.c:5801
msgid "unrecognized relocation suffix"
msgstr ""
-#: config/tc-arm.c:2990
+#: config/tc-arm.c:2986
msgid "(plt) is only valid on branch targets"
msgstr ""
-#: config/tc-arm.c:2996 config/tc-s390.c:1129 config/tc-s390.c:1743
+#: config/tc-arm.c:2992 config/tc-s390.c:1129 config/tc-s390.c:1743
#: config/tc-xtensa.c:1546
#, c-format
msgid "%s relocations do not fit in %d bytes"
msgstr ""
-#: config/tc-arm.c:3044 dwarf2dbg.c:694
+#: config/tc-arm.c:3040 dwarf2dbg.c:694
msgid "expected 0 or 1"
msgstr ""
-#: config/tc-arm.c:3048
+#: config/tc-arm.c:3044
msgid "missing comma"
msgstr ""
-#: config/tc-arm.c:3103
+#: config/tc-arm.c:3099
msgid "duplicate .handlerdata directive"
msgstr ""
-#: config/tc-arm.c:3174
+#: config/tc-arm.c:3171
msgid "personality routine specified for cantunwind frame"
msgstr ""
-#: config/tc-arm.c:3188
+#: config/tc-arm.c:3185
msgid "duplicate .personalityindex directive"
msgstr ""
-#: config/tc-arm.c:3195
+#: config/tc-arm.c:3192
msgid "bad personality routine number"
msgstr ""
-#: config/tc-arm.c:3214
+#: config/tc-arm.c:3211
msgid "duplicate .personality directive"
msgstr ""
-#: config/tc-arm.c:3237 config/tc-arm.c:3365 config/tc-arm.c:3413
+#: config/tc-arm.c:3234 config/tc-arm.c:3362 config/tc-arm.c:3410
msgid "expected register list"
msgstr ""
-#: config/tc-arm.c:3319
+#: config/tc-arm.c:3316
msgid "expected , <constant>"
msgstr ""
-#: config/tc-arm.c:3328
+#: config/tc-arm.c:3325
msgid "number of registers must be in the range [1:4]"
msgstr ""
-#: config/tc-arm.c:3475 config/tc-arm.c:3608
+#: config/tc-arm.c:3472 config/tc-arm.c:3605
msgid "bad register range"
msgstr ""
-#: config/tc-arm.c:3662
+#: config/tc-arm.c:3659
msgid "register expected"
msgstr ""
-#: config/tc-arm.c:3672
+#: config/tc-arm.c:3669
msgid "FPA .unwind_save does not take a register list"
msgstr ""
-#: config/tc-arm.c:3690
+#: config/tc-arm.c:3687
msgid ".unwind_save does not support this kind of register"
msgstr ""
-#: config/tc-arm.c:3726
+#: config/tc-arm.c:3723
msgid "SP and PC not permitted in .unwind_movsp directive"
msgstr ""
-#: config/tc-arm.c:3731
+#: config/tc-arm.c:3728
msgid "unexpected .unwind_movsp directive"
msgstr ""
-#: config/tc-arm.c:3755
+#: config/tc-arm.c:3752
msgid "stack increment must be multiple of 4"
msgstr ""
-#: config/tc-arm.c:3784
+#: config/tc-arm.c:3781
msgid "expected <reg>, <reg>"
msgstr ""
-#: config/tc-arm.c:3802
+#: config/tc-arm.c:3799
msgid "register must be either sp or set by a previousunwind_movsp directive"
msgstr ""
-#: config/tc-arm.c:3838
+#: config/tc-arm.c:3835
msgid "expected <offset>, <opcode>"
msgstr ""
-#: config/tc-arm.c:3850
+#: config/tc-arm.c:3847
msgid "unwind opcode too long"
msgstr ""
-#: config/tc-arm.c:3855
+#: config/tc-arm.c:3852
msgid "invalid unwind opcode"
msgstr ""
-#: config/tc-arm.c:4002 config/tc-arm.c:4865 config/tc-arm.c:8440
-#: config/tc-arm.c:8922 config/tc-arm.c:11720 config/tc-arm.c:18692
-#: config/tc-arm.c:18717 config/tc-arm.c:18725 config/tc-z8k.c:1144
+#: config/tc-arm.c:3999 config/tc-arm.c:4861 config/tc-arm.c:8434
+#: config/tc-arm.c:8916 config/tc-arm.c:11712 config/tc-arm.c:18684
+#: config/tc-arm.c:18709 config/tc-arm.c:18717 config/tc-z8k.c:1144
#: config/tc-z8k.c:1154
msgid "immediate value out of range"
msgstr ""
-#: config/tc-arm.c:4149
+#: config/tc-arm.c:4146
msgid "invalid FPA immediate expression"
msgstr ""
-#: config/tc-arm.c:4273 config/tc-arm.c:4281
+#: config/tc-arm.c:4270 config/tc-arm.c:4278
msgid "shift expression expected"
msgstr ""
-#: config/tc-arm.c:4295
+#: config/tc-arm.c:4292
msgid "'LSL' or 'ASR' required"
msgstr ""
-#: config/tc-arm.c:4303
+#: config/tc-arm.c:4300
msgid "'LSL' required"
msgstr ""
-#: config/tc-arm.c:4311
+#: config/tc-arm.c:4308
msgid "'ASR' required"
msgstr ""
-#: config/tc-arm.c:4383 config/tc-arm.c:4859 config/tc-arm.c:6431
+#: config/tc-arm.c:4380 config/tc-arm.c:4855 config/tc-arm.c:6427
#: config/tc-v850.c:1827 config/tc-v850.c:1848
msgid "constant expression expected"
msgstr ""
-#: config/tc-arm.c:4390
+#: config/tc-arm.c:4387
msgid "invalid rotation"
msgstr ""
-#: config/tc-arm.c:4550 config/tc-arm.c:4695
+#: config/tc-arm.c:4547 config/tc-arm.c:4691
msgid "unknown group relocation"
msgstr ""
-#: config/tc-arm.c:4663
+#: config/tc-arm.c:4660
msgid "alignment must be constant"
msgstr ""
-#: config/tc-arm.c:4726
+#: config/tc-arm.c:4722
msgid "this group relocation is not allowed on this instruction"
msgstr ""
-#: config/tc-arm.c:4738 config/tc-arm.c:5129
+#: config/tc-arm.c:4734 config/tc-arm.c:5125
msgid "']' expected"
msgstr ""
-#: config/tc-arm.c:4756
+#: config/tc-arm.c:4752
msgid "'}' expected at end of 'option' field"
msgstr ""
-#: config/tc-arm.c:4761
+#: config/tc-arm.c:4757
msgid "cannot combine index with option"
msgstr ""
-#: config/tc-arm.c:4774
+#: config/tc-arm.c:4770
msgid "cannot combine pre- and post-indexing"
msgstr ""
-#: config/tc-arm.c:4935
+#: config/tc-arm.c:4931
msgid "flag for {c}psr instruction expected"
msgstr ""
-#: config/tc-arm.c:4960
+#: config/tc-arm.c:4956
msgid "unrecognized CPS flag"
msgstr ""
-#: config/tc-arm.c:4967
+#: config/tc-arm.c:4963
msgid "missing CPS flags"
msgstr ""
-#: config/tc-arm.c:4990 config/tc-arm.c:4996
+#: config/tc-arm.c:4986 config/tc-arm.c:4992
msgid "valid endian specifiers are be or le"
msgstr ""
-#: config/tc-arm.c:5018
+#: config/tc-arm.c:5014
msgid "missing rotation field after comma"
msgstr ""
-#: config/tc-arm.c:5033
+#: config/tc-arm.c:5029
msgid "rotation can only be 0, 8, 16, or 24"
msgstr ""
-#: config/tc-arm.c:5053
+#: config/tc-arm.c:5049
msgid "condition required"
msgstr ""
-#: config/tc-arm.c:5091 config/tc-arm.c:6926
+#: config/tc-arm.c:5087 config/tc-arm.c:6922
msgid "'[' expected"
msgstr ""
-#: config/tc-arm.c:5104
+#: config/tc-arm.c:5100
msgid "',' expected"
msgstr ""
-#: config/tc-arm.c:5121
+#: config/tc-arm.c:5117
msgid "invalid shift"
msgstr ""
-#: config/tc-arm.c:5194
+#: config/tc-arm.c:5190
msgid "can't use Neon quad register here"
msgstr ""
-#: config/tc-arm.c:5260
+#: config/tc-arm.c:5256
msgid "expected <Rm> or <Dm> or <Qm> operand"
msgstr ""
-#: config/tc-arm.c:5340
+#: config/tc-arm.c:5336
msgid "parse error"
msgstr ""
-#: config/tc-arm.c:5350 read.c:2096
+#: config/tc-arm.c:5346 read.c:2096
msgid "expected comma"
msgstr ""
-#: config/tc-arm.c:5640 config/tc-arm.c:5710
+#: config/tc-arm.c:5636 config/tc-arm.c:5706
msgid "immediate value is out of range"
msgstr ""
-#: config/tc-arm.c:5855
+#: config/tc-arm.c:5851
msgid "iWMMXt data or control register expected"
msgstr ""
-#: config/tc-arm.c:6008
+#: config/tc-arm.c:6004
#, c-format
msgid "unhandled operand code %d"
msgstr ""
-#: config/tc-arm.c:6087 config/tc-score.c:56
+#: config/tc-arm.c:6083 config/tc-score.c:56
msgid "garbage following instruction"
msgstr ""
-#: config/tc-arm.c:6174
+#: config/tc-arm.c:6170
msgid "D register out of range for selected VFP version"
msgstr ""
-#: config/tc-arm.c:6253
+#: config/tc-arm.c:6249
msgid "instruction does not accept preindexed addressing"
msgstr ""
#. unindexed - only for coprocessor
-#: config/tc-arm.c:6269 config/tc-arm.c:8246
+#: config/tc-arm.c:6265 config/tc-arm.c:8240
msgid "instruction does not accept unindexed addressing"
msgstr ""
-#: config/tc-arm.c:6277
+#: config/tc-arm.c:6273
msgid "destination register same as write-back base"
msgstr ""
-#: config/tc-arm.c:6278
+#: config/tc-arm.c:6274
msgid "source register same as write-back base"
msgstr ""
-#: config/tc-arm.c:6324
+#: config/tc-arm.c:6320
msgid "instruction does not accept scaled register index"
msgstr ""
-#: config/tc-arm.c:6364
+#: config/tc-arm.c:6360
msgid "instruction does not support unindexed addressing"
msgstr ""
-#: config/tc-arm.c:6379
+#: config/tc-arm.c:6375
msgid "pc may not be used with write-back"
msgstr ""
-#: config/tc-arm.c:6384
+#: config/tc-arm.c:6380
msgid "instruction does not support writeback"
msgstr ""
-#: config/tc-arm.c:6426
+#: config/tc-arm.c:6422
msgid "invalid pseudo operation"
msgstr ""
-#: config/tc-arm.c:6472
+#: config/tc-arm.c:6468
msgid "literal pool insertion failed"
msgstr ""
-#: config/tc-arm.c:6530
+#: config/tc-arm.c:6526
msgid "Rn must not overlap other operands"
msgstr ""
-#: config/tc-arm.c:6619 config/tc-arm.c:8778
+#: config/tc-arm.c:6615 config/tc-arm.c:8772
msgid "bad barrier type"
msgstr ""
-#: config/tc-arm.c:6630 config/tc-arm.c:6649 config/tc-arm.c:6662
-#: config/tc-arm.c:8789 config/tc-arm.c:8809 config/tc-arm.c:8823
+#: config/tc-arm.c:6626 config/tc-arm.c:6645 config/tc-arm.c:6658
+#: config/tc-arm.c:8783 config/tc-arm.c:8803 config/tc-arm.c:8817
msgid "bit-field extends past end of register"
msgstr ""
-#: config/tc-arm.c:6691
+#: config/tc-arm.c:6687
msgid "the only suffix valid here is '(plt)'"
msgstr ""
-#: config/tc-arm.c:6744
+#: config/tc-arm.c:6740
msgid "use of r15 in blx in ARM mode is not really useful"
msgstr ""
-#: config/tc-arm.c:6767
+#: config/tc-arm.c:6763
msgid "use of r15 in bx in ARM mode is not really useful"
msgstr ""
-#: config/tc-arm.c:6779 config/tc-arm.c:8961
+#: config/tc-arm.c:6775 config/tc-arm.c:8955
msgid "use of r15 in bxj is not really useful"
msgstr ""
-#: config/tc-arm.c:6893 config/tc-arm.c:6902
+#: config/tc-arm.c:6889 config/tc-arm.c:6898
msgid "writeback of base register is UNPREDICTABLE"
msgstr ""
-#: config/tc-arm.c:6896
+#: config/tc-arm.c:6892
msgid "writeback of base register when in register list is UNPREDICTABLE"
msgstr ""
-#: config/tc-arm.c:6906
+#: config/tc-arm.c:6902
msgid "if writeback register is in list, it must be the lowest reg in the list"
msgstr ""
-#: config/tc-arm.c:6921
+#: config/tc-arm.c:6917
msgid "first destination register must be even"
msgstr ""
-#: config/tc-arm.c:6924 config/tc-arm.c:6991
+#: config/tc-arm.c:6920 config/tc-arm.c:6987
msgid "can only load two consecutive registers"
msgstr ""
#. have been called in the first place.
#. If op 2 were present and equal to PC, this function wouldn't
#. have been called in the first place.
-#: config/tc-arm.c:6925 config/tc-arm.c:6994 config/tc-arm.c:7516
-#: config/tc-arm.c:9439
+#: config/tc-arm.c:6921 config/tc-arm.c:6990 config/tc-arm.c:7512
+#: config/tc-arm.c:9433
msgid "r14 not allowed here"
msgstr ""
-#: config/tc-arm.c:6939
+#: config/tc-arm.c:6935
msgid "base register written back, and overlaps second destination register"
msgstr ""
-#: config/tc-arm.c:6947
+#: config/tc-arm.c:6943
msgid "index register overlaps destination register"
msgstr ""
-#: config/tc-arm.c:6977 config/tc-arm.c:7498
+#: config/tc-arm.c:6973 config/tc-arm.c:7494
msgid "offset must be zero in ARM encoding"
msgstr ""
-#: config/tc-arm.c:6988 config/tc-arm.c:7510
+#: config/tc-arm.c:6984 config/tc-arm.c:7506
msgid "even register required"
msgstr ""
-#: config/tc-arm.c:7019 config/tc-arm.c:7050
+#: config/tc-arm.c:7015 config/tc-arm.c:7046
msgid "this instruction requires a post-indexed address"
msgstr ""
-#: config/tc-arm.c:7077
+#: config/tc-arm.c:7073
msgid "Rd and Rm should be different in mla"
msgstr ""
-#: config/tc-arm.c:7101 config/tc-arm.c:9697
+#: config/tc-arm.c:7097 config/tc-arm.c:9690
msgid ":lower16: not allowed this instruction"
msgstr ""
-#: config/tc-arm.c:7103
+#: config/tc-arm.c:7099
msgid ":upper16: not allowed instruction"
msgstr ""
-#: config/tc-arm.c:7122
+#: config/tc-arm.c:7118
msgid "operand 1 must be FPSCR"
msgstr ""
-#: config/tc-arm.c:7155 config/tc-arm.c:9806
+#: config/tc-arm.c:7151 config/tc-arm.c:9799
msgid "'CPSR' or 'SPSR' expected"
msgstr ""
-#: config/tc-arm.c:7192
+#: config/tc-arm.c:7188
msgid "Rd and Rm should be different in mul"
msgstr ""
-#: config/tc-arm.c:7213
+#: config/tc-arm.c:7209
msgid "rdhi, rdlo and rm must all be different"
msgstr ""
-#: config/tc-arm.c:7275
+#: config/tc-arm.c:7271
msgid "'[' expected after PLD mnemonic"
msgstr ""
-#: config/tc-arm.c:7277 config/tc-arm.c:7292
+#: config/tc-arm.c:7273 config/tc-arm.c:7288
msgid "post-indexed expression used in preload instruction"
msgstr ""
-#: config/tc-arm.c:7279 config/tc-arm.c:7294
+#: config/tc-arm.c:7275 config/tc-arm.c:7290
msgid "writeback used in preload instruction"
msgstr ""
-#: config/tc-arm.c:7281 config/tc-arm.c:7296
+#: config/tc-arm.c:7277 config/tc-arm.c:7292
msgid "unindexed addressing used in preload instruction"
msgstr ""
-#: config/tc-arm.c:7290
+#: config/tc-arm.c:7286
msgid "'[' expected after PLI mnemonic"
msgstr ""
-#: config/tc-arm.c:7443 config/tc-arm.c:9886
+#: config/tc-arm.c:7439 config/tc-arm.c:9879
msgid "rdhi and rdlo must be different"
msgstr ""
-#: config/tc-arm.c:7469
+#: config/tc-arm.c:7465
msgid "SRS base register must be r13"
msgstr ""
-#: config/tc-arm.c:7513
+#: config/tc-arm.c:7509
msgid "can only store two consecutive registers"
msgstr ""
-#: config/tc-arm.c:7608 config/tc-arm.c:7625
+#: config/tc-arm.c:7604 config/tc-arm.c:7621
msgid "only two consecutive VFP SP registers allowed here"
msgstr ""
-#: config/tc-arm.c:7653 config/tc-arm.c:7668
+#: config/tc-arm.c:7649 config/tc-arm.c:7664
msgid "this addressing mode requires base-register writeback"
msgstr ""
-#: config/tc-arm.c:7843
+#: config/tc-arm.c:7838
msgid "this instruction does not support indexing"
msgstr ""
-#: config/tc-arm.c:7867
+#: config/tc-arm.c:7861
msgid "only r15 allowed here"
msgstr ""
-#: config/tc-arm.c:8002
+#: config/tc-arm.c:7996
msgid "immediate operand requires iWMMXt2"
msgstr ""
-#: config/tc-arm.c:8146
+#: config/tc-arm.c:8140
msgid "shift by register not allowed in thumb mode"
msgstr ""
-#: config/tc-arm.c:8158 config/tc-arm.c:18199
+#: config/tc-arm.c:8152 config/tc-arm.c:18191
msgid "shift expression is too large"
msgstr ""
-#: config/tc-arm.c:8184
+#: config/tc-arm.c:8178
msgid "Instruction does not support =N addresses"
msgstr ""
-#: config/tc-arm.c:8189
+#: config/tc-arm.c:8183
msgid "cannot use register index with PC-relative addressing"
msgstr ""
-#: config/tc-arm.c:8190
+#: config/tc-arm.c:8184
msgid "cannot use register index with this instruction"
msgstr ""
-#: config/tc-arm.c:8192
+#: config/tc-arm.c:8186
msgid "Thumb does not support negative register indexing"
msgstr ""
-#: config/tc-arm.c:8194
+#: config/tc-arm.c:8188
msgid "Thumb does not support register post-indexing"
msgstr ""
-#: config/tc-arm.c:8196
+#: config/tc-arm.c:8190
msgid "Thumb does not support register indexing with writeback"
msgstr ""
-#: config/tc-arm.c:8198
+#: config/tc-arm.c:8192
msgid "Thumb supports only LSL in shifted register indexing"
msgstr ""
-#: config/tc-arm.c:8207 config/tc-arm.c:12948
+#: config/tc-arm.c:8201 config/tc-arm.c:12938
msgid "shift out of range"
msgstr ""
-#: config/tc-arm.c:8215
+#: config/tc-arm.c:8209
msgid "cannot use writeback with PC-relative addressing"
msgstr ""
-#: config/tc-arm.c:8217
+#: config/tc-arm.c:8211
msgid "cannot use writeback with this instruction"
msgstr ""
-#: config/tc-arm.c:8236
+#: config/tc-arm.c:8230
msgid "cannot use post-indexing with PC-relative addressing"
msgstr ""
-#: config/tc-arm.c:8237
+#: config/tc-arm.c:8231
msgid "cannot use post-indexing with this instruction"
msgstr ""
-#: config/tc-arm.c:8364
+#: config/tc-arm.c:8358
msgid "PC not allowed as destination"
msgstr ""
-#: config/tc-arm.c:8435
+#: config/tc-arm.c:8429
msgid "only SUBS PC, LR, #const allowed"
msgstr ""
-#: config/tc-arm.c:8508 config/tc-arm.c:8649 config/tc-arm.c:8741
-#: config/tc-arm.c:9761
+#: config/tc-arm.c:8502 config/tc-arm.c:8643 config/tc-arm.c:8735
+#: config/tc-arm.c:9754
msgid "shift must be constant"
msgstr ""
-#: config/tc-arm.c:8535 config/tc-arm.c:8664 config/tc-arm.c:8756
-#: config/tc-arm.c:9774
+#: config/tc-arm.c:8529 config/tc-arm.c:8658 config/tc-arm.c:8750
+#: config/tc-arm.c:9767
msgid "unshifted register required"
msgstr ""
-#: config/tc-arm.c:8550 config/tc-arm.c:8767 config/tc-arm.c:9873
+#: config/tc-arm.c:8544 config/tc-arm.c:8761 config/tc-arm.c:9866
msgid "dest must overlap one source register"
msgstr ""
-#: config/tc-arm.c:8667
+#: config/tc-arm.c:8661
msgid "dest and source1 must be the same register"
msgstr ""
-#: config/tc-arm.c:8918
+#: config/tc-arm.c:8912
msgid "instruction is always unconditional"
msgstr ""
-#: config/tc-arm.c:9000
+#: config/tc-arm.c:8994
msgid "selected processor does not support 'A' form of this instruction"
msgstr ""
-#: config/tc-arm.c:9003
+#: config/tc-arm.c:8997
msgid "Thumb does not support the 2-argument form of this instruction"
msgstr ""
-#: config/tc-arm.c:9102
+#: config/tc-arm.c:9096
msgid "SP not allowed in register list"
msgstr ""
-#: config/tc-arm.c:9107
+#: config/tc-arm.c:9101
msgid "LR and PC should not both be in register list"
msgstr ""
-#: config/tc-arm.c:9111
+#: config/tc-arm.c:9105
msgid "base register should not be in register list when written back"
msgstr ""
-#: config/tc-arm.c:9117
+#: config/tc-arm.c:9111
msgid "PC not allowed in register list"
msgstr ""
-#: config/tc-arm.c:9120 config/tc-arm.c:9186 config/tc-arm.c:9226
+#: config/tc-arm.c:9114 config/tc-arm.c:9180 config/tc-arm.c:9220
#, c-format
msgid "value stored for r%d is UNPREDICTABLE"
msgstr ""
-#: config/tc-arm.c:9162
+#: config/tc-arm.c:9156
msgid "Thumb load/store multiple does not support {reglist}^"
msgstr ""
-#: config/tc-arm.c:9219
+#: config/tc-arm.c:9213
msgid "Thumb-2 instruction only valid in unified syntax"
msgstr ""
-#: config/tc-arm.c:9223 config/tc-arm.c:9233
+#: config/tc-arm.c:9217 config/tc-arm.c:9227
msgid "this instruction will write back the base register"
msgstr ""
-#: config/tc-arm.c:9236
+#: config/tc-arm.c:9230
msgid "this instruction will not write back the base register"
msgstr ""
-#: config/tc-arm.c:9265
+#: config/tc-arm.c:9259
msgid "r14 not allowed as first register when second register is omitted"
msgstr ""
-#: config/tc-arm.c:9362 config/tc-arm.c:9375 config/tc-arm.c:9411
+#: config/tc-arm.c:9356 config/tc-arm.c:9369 config/tc-arm.c:9405
msgid "Thumb does not support this addressing mode"
msgstr ""
-#: config/tc-arm.c:9379
+#: config/tc-arm.c:9373
msgid "byte or halfword not valid for base register"
msgstr ""
-#: config/tc-arm.c:9382
+#: config/tc-arm.c:9376
msgid "r15 based store not allowed"
msgstr ""
-#: config/tc-arm.c:9384
+#: config/tc-arm.c:9378
msgid "invalid base register for register offset"
msgstr ""
-#: config/tc-arm.c:9682
+#: config/tc-arm.c:9675
msgid "only lo regs allowed with immediate"
msgstr ""
-#: config/tc-arm.c:9702
+#: config/tc-arm.c:9695
msgid ":upper16: not allowed this instruction"
msgstr ""
-#: config/tc-arm.c:9796 config/tc-arm.c:9828 config/tc-arm.c:9834
+#: config/tc-arm.c:9789 config/tc-arm.c:9821 config/tc-arm.c:9827
msgid "selected processor does not support requested special purpose register"
msgstr ""
-#: config/tc-arm.c:9802
+#: config/tc-arm.c:9795
#, c-format
msgid ""
"selected processor does not support requested special purpose register %x"
msgstr ""
-#: config/tc-arm.c:9823
+#: config/tc-arm.c:9816
msgid "Thumb encoding does not support an immediate here"
msgstr ""
-#: config/tc-arm.c:9908
+#: config/tc-arm.c:9901
msgid "Thumb does not support NOP with hints"
msgstr ""
-#: config/tc-arm.c:9990
+#: config/tc-arm.c:9983
msgid "push/pop do not support {reglist}^"
msgstr ""
-#: config/tc-arm.c:10013
+#: config/tc-arm.c:10006
msgid "invalid register list to push/pop instruction"
msgstr ""
-#: config/tc-arm.c:10205
+#: config/tc-arm.c:10198
msgid "source1 and dest must be same register"
msgstr ""
-#: config/tc-arm.c:10226
+#: config/tc-arm.c:10219
msgid "ror #imm not supported"
msgstr ""
-#: config/tc-arm.c:10351
+#: config/tc-arm.c:10344
msgid "Thumb encoding does not support rotation"
msgstr ""
-#: config/tc-arm.c:10370
+#: config/tc-arm.c:10363
msgid "instruction requires register index"
msgstr ""
-#: config/tc-arm.c:10372
+#: config/tc-arm.c:10365
msgid "PC is not a valid index register"
msgstr ""
-#: config/tc-arm.c:10374
+#: config/tc-arm.c:10367
msgid "instruction does not allow shifted index"
msgstr ""
-#: config/tc-arm.c:10793
+#: config/tc-arm.c:10785
msgid "invalid instruction shape"
msgstr ""
-#: config/tc-arm.c:11035
+#: config/tc-arm.c:11027
msgid "types specified in both the mnemonic and operands"
msgstr ""
-#: config/tc-arm.c:11072
+#: config/tc-arm.c:11064
msgid "operand types can't be inferred"
msgstr ""
-#: config/tc-arm.c:11078
+#: config/tc-arm.c:11070
msgid "type specifier has the wrong number of parts"
msgstr ""
-#: config/tc-arm.c:11133
+#: config/tc-arm.c:11125
msgid "operand size must match register width"
msgstr ""
-#: config/tc-arm.c:11144
+#: config/tc-arm.c:11136
msgid "bad type in Neon instruction"
msgstr ""
-#: config/tc-arm.c:11155
+#: config/tc-arm.c:11147
msgid "inconsistent types in Neon instruction"
msgstr ""
-#: config/tc-arm.c:12204
+#: config/tc-arm.c:12196
msgid "scalar out of range for multiply instruction"
msgstr ""
-#: config/tc-arm.c:12368 config/tc-arm.c:12380
+#: config/tc-arm.c:12360 config/tc-arm.c:12372
msgid "immediate out of range for insert"
msgstr ""
-#: config/tc-arm.c:12392 config/tc-arm.c:13294
+#: config/tc-arm.c:12384 config/tc-arm.c:13283
msgid "immediate out of range for shift"
msgstr ""
-#: config/tc-arm.c:12449 config/tc-arm.c:12476 config/tc-arm.c:12794
-#: config/tc-arm.c:13240
+#: config/tc-arm.c:12441 config/tc-arm.c:12468 config/tc-arm.c:12786
+#: config/tc-arm.c:13229
msgid "immediate out of range"
msgstr ""
-#: config/tc-arm.c:12513
+#: config/tc-arm.c:12505
msgid "immediate out of range for narrowing operation"
msgstr ""
-#: config/tc-arm.c:12633
+#: config/tc-arm.c:12625
msgid "operands 0 and 1 must be the same register"
msgstr ""
-#: config/tc-arm.c:12768
+#: config/tc-arm.c:12760
msgid "operand size must be specified for immediate VMOV"
msgstr ""
-#: config/tc-arm.c:12778
+#: config/tc-arm.c:12770
msgid "immediate has bits set outside the operand size"
msgstr ""
-#: config/tc-arm.c:12974
+#: config/tc-arm.c:12964
msgid "elements must be smaller than reversal region"
msgstr ""
-#: config/tc-arm.c:13145 config/tc-arm.c:13193
+#: config/tc-arm.c:13134 config/tc-arm.c:13182
msgid "bad type for scalar"
msgstr ""
-#: config/tc-arm.c:13257 config/tc-arm.c:13265
+#: config/tc-arm.c:13246 config/tc-arm.c:13254
msgid "VFP registers must be adjacent"
msgstr ""
-#: config/tc-arm.c:13406
+#: config/tc-arm.c:13395
msgid "bad list length for table lookup"
msgstr ""
-#: config/tc-arm.c:13436
+#: config/tc-arm.c:13425
msgid "writeback (!) must be used for VLDMDB and VSTMDB"
msgstr ""
-#: config/tc-arm.c:13439
+#: config/tc-arm.c:13428
msgid "register list must contain at least 1 and at most 16 registers"
msgstr ""
-#: config/tc-arm.c:13516
+#: config/tc-arm.c:13505
msgid "bad alignment"
msgstr ""
-#: config/tc-arm.c:13533
+#: config/tc-arm.c:13522
msgid "bad list type for instruction"
msgstr ""
-#: config/tc-arm.c:13575
+#: config/tc-arm.c:13564
msgid "unsupported alignment for instruction"
msgstr ""
-#: config/tc-arm.c:13594 config/tc-arm.c:13688 config/tc-arm.c:13699
-#: config/tc-arm.c:13709 config/tc-arm.c:13723
+#: config/tc-arm.c:13583 config/tc-arm.c:13677 config/tc-arm.c:13688
+#: config/tc-arm.c:13698 config/tc-arm.c:13712
msgid "bad list length"
msgstr ""
-#: config/tc-arm.c:13599
+#: config/tc-arm.c:13588
msgid "stride of 2 unavailable when element size is 8"
msgstr ""
-#: config/tc-arm.c:13632 config/tc-arm.c:13707
+#: config/tc-arm.c:13621 config/tc-arm.c:13696
msgid "can't use alignment with this instruction"
msgstr ""
-#: config/tc-arm.c:13771
+#: config/tc-arm.c:13760
msgid "post-index must be a register"
msgstr ""
-#: config/tc-arm.c:13773
+#: config/tc-arm.c:13762
msgid "bad register for post-index"
msgstr ""
-#: config/tc-arm.c:14060 config/tc-arm.c:14146
+#: config/tc-arm.c:14049 config/tc-arm.c:14135
msgid "conditional infixes are deprecated in unified syntax"
msgstr ""
-#: config/tc-arm.c:14185
+#: config/tc-arm.c:14174
msgid "s suffix on comparison instruction is deprecated"
msgstr ""
-#: config/tc-arm.c:14204 config/tc-arm.c:14285
+#: config/tc-arm.c:14193 config/tc-arm.c:14274
#, c-format
msgid "selected processor does not support `%s'"
msgstr ""
-#: config/tc-arm.c:14210
+#: config/tc-arm.c:14199
msgid "Thumb does not support conditional execution"
msgstr ""
-#: config/tc-arm.c:14233
+#: config/tc-arm.c:14222
msgid "incorrect condition in IT block"
msgstr ""
-#: config/tc-arm.c:14239
+#: config/tc-arm.c:14228
msgid "thumb conditional instruction not in IT block"
msgstr ""
-#: config/tc-arm.c:14259
+#: config/tc-arm.c:14248
#, c-format
msgid "cannot honor width suffix -- `%s'"
msgstr ""
-#: config/tc-arm.c:14290
+#: config/tc-arm.c:14279
#, c-format
msgid "width suffixes are invalid in ARM mode -- `%s'"
msgstr ""
-#: config/tc-arm.c:14314
+#: config/tc-arm.c:14303
#, c-format
msgid "attempt to use an ARM instruction on a Thumb-only processor -- `%s'"
msgstr ""
-#: config/tc-arm.c:17065
+#: config/tc-arm.c:17057
msgid "alignments greater than 32 bytes not supported in .text sections."
msgstr ""
-#: config/tc-arm.c:17314 config/tc-ia64.c:3756
+#: config/tc-arm.c:17306 config/tc-ia64.c:3756
#, c-format
msgid "Group section `%s' has no group signature"
msgstr ""
-#: config/tc-arm.c:17359
-msgid "handerdata in cantunwind frame"
+#: config/tc-arm.c:17351
+msgid "handlerdata in cantunwind frame"
msgstr ""
-#: config/tc-arm.c:17376
+#: config/tc-arm.c:17368
msgid "too many unwind opcodes for personality routine 0"
msgstr ""
-#: config/tc-arm.c:17408
+#: config/tc-arm.c:17400
msgid "too many unwind opcodes"
msgstr ""
-#: config/tc-arm.c:17632
+#: config/tc-arm.c:17624
msgid "GOT already in the symbol table"
msgstr ""
-#: config/tc-arm.c:17942 config/tc-arm.c:18226
+#: config/tc-arm.c:17934 config/tc-arm.c:18218
#, c-format
msgid "undefined symbol %s used as an immediate value"
msgstr ""
-#: config/tc-arm.c:17956 config/tc-arm.c:18265
+#: config/tc-arm.c:17948 config/tc-arm.c:18257
#, c-format
msgid "invalid constant (%lx) after fixup"
msgstr ""
-#: config/tc-arm.c:17993
+#: config/tc-arm.c:17985
#, c-format
msgid "unable to compute ADRL instructions for PC offset of 0x%lx"
msgstr ""
-#: config/tc-arm.c:18028 config/tc-arm.c:18053
+#: config/tc-arm.c:18020 config/tc-arm.c:18045
msgid "invalid literal constant: pool needs to be closer"
msgstr ""
-#: config/tc-arm.c:18031 config/tc-arm.c:18069
+#: config/tc-arm.c:18023 config/tc-arm.c:18061
#, c-format
msgid "bad immediate value for offset (%ld)"
msgstr ""
-#: config/tc-arm.c:18055
+#: config/tc-arm.c:18047
#, c-format
msgid "bad immediate value for 8-bit offset (%ld)"
msgstr ""
-#: config/tc-arm.c:18110
+#: config/tc-arm.c:18102
msgid "offset not a multiple of 4"
msgstr ""
-#: config/tc-arm.c:18117 config/tc-arm.c:18132 config/tc-arm.c:18147
-#: config/tc-arm.c:18158 config/tc-arm.c:18181 config/tc-arm.c:18776
+#: config/tc-arm.c:18109 config/tc-arm.c:18124 config/tc-arm.c:18139
+#: config/tc-arm.c:18150 config/tc-arm.c:18173 config/tc-arm.c:18768
#: config/tc-pj.c:450 config/tc-sh.c:4164
msgid "offset out of range"
msgstr ""
-#: config/tc-arm.c:18281
+#: config/tc-arm.c:18273
msgid "invalid smc expression"
msgstr ""
-#: config/tc-arm.c:18292 config/tc-arm.c:18301
+#: config/tc-arm.c:18284 config/tc-arm.c:18293
msgid "invalid swi expression"
msgstr ""
-#: config/tc-arm.c:18311
+#: config/tc-arm.c:18303
msgid "invalid expression in load/store multiple"
msgstr ""
-#: config/tc-arm.c:18341
+#: config/tc-arm.c:18333
msgid "misaligned branch destination"
msgstr ""
-#: config/tc-arm.c:18345 config/tc-arm.c:18382 config/tc-arm.c:18396
-#: config/tc-arm.c:18409 config/tc-arm.c:18448 config/tc-arm.c:18473
+#: config/tc-arm.c:18337 config/tc-arm.c:18374 config/tc-arm.c:18388
+#: config/tc-arm.c:18401 config/tc-arm.c:18440 config/tc-arm.c:18465
msgid "branch out of range"
msgstr ""
-#: config/tc-arm.c:18422
+#: config/tc-arm.c:18414
msgid "conditional branch out of range"
msgstr ""
-#: config/tc-arm.c:18550
+#: config/tc-arm.c:18542
msgid "rel31 relocation overflow"
msgstr ""
-#: config/tc-arm.c:18562 config/tc-arm.c:18585
+#: config/tc-arm.c:18554 config/tc-arm.c:18577
msgid "co-processor offset out of range"
msgstr ""
-#: config/tc-arm.c:18602
+#: config/tc-arm.c:18594
#, c-format
msgid "invalid offset, target not word aligned (0x%08lX)"
msgstr ""
-#: config/tc-arm.c:18609 config/tc-arm.c:18618 config/tc-arm.c:18626
-#: config/tc-arm.c:18634 config/tc-arm.c:18642
+#: config/tc-arm.c:18601 config/tc-arm.c:18610 config/tc-arm.c:18618
+#: config/tc-arm.c:18626 config/tc-arm.c:18634
#, c-format
msgid "invalid offset, value too big (0x%08lX)"
msgstr ""
-#: config/tc-arm.c:18683
+#: config/tc-arm.c:18675
msgid "invalid Hi register with immediate"
msgstr ""
-#: config/tc-arm.c:18699
+#: config/tc-arm.c:18691
msgid "invalid immediate for stack address calculation"
msgstr ""
-#: config/tc-arm.c:18707
+#: config/tc-arm.c:18699
#, c-format
msgid "invalid immediate for address calculation (value = 0x%08lX)"
msgstr ""
-#: config/tc-arm.c:18737
+#: config/tc-arm.c:18729
#, c-format
msgid "invalid immediate: %ld is out of range"
msgstr ""
-#: config/tc-arm.c:18749
+#: config/tc-arm.c:18741
#, c-format
msgid "invalid shift value: %ld"
msgstr ""
-#: config/tc-arm.c:18828
+#: config/tc-arm.c:18820
#, c-format
msgid "the offset 0x%08lX is not representable"
msgstr ""
-#: config/tc-arm.c:18868
+#: config/tc-arm.c:18860
#, c-format
msgid "bad offset 0x%08lX (only 12 bits available for the magnitude)"
msgstr ""
-#: config/tc-arm.c:18907
+#: config/tc-arm.c:18899
#, c-format
msgid "bad offset 0x%08lX (only 8 bits available for the magnitude)"
msgstr ""
-#: config/tc-arm.c:18947
+#: config/tc-arm.c:18939
#, c-format
msgid "bad offset 0x%08lX (must be word-aligned)"
msgstr ""
-#: config/tc-arm.c:18952
+#: config/tc-arm.c:18944
#, c-format
msgid "bad offset 0x%08lX (must be an 8-bit number of words)"
msgstr ""
-#: config/tc-arm.c:18978 config/tc-score.c:5410
+#: config/tc-arm.c:18970 config/tc-score.c:5410
#, c-format
msgid "bad relocation fixup type (%d)"
msgstr ""
-#: config/tc-arm.c:19081
+#: config/tc-arm.c:19073
msgid "literal referenced across section boundary"
msgstr ""
-#: config/tc-arm.c:19141
+#: config/tc-arm.c:19133
msgid "internal relocation (type: IMMEDIATE) not fixed up"
msgstr ""
-#: config/tc-arm.c:19146
+#: config/tc-arm.c:19138
msgid "ADRL used for a symbol not defined in the same file"
msgstr ""
-#: config/tc-arm.c:19161
+#: config/tc-arm.c:19153
#, c-format
msgid "undefined local label `%s'"
msgstr ""
-#: config/tc-arm.c:19167
+#: config/tc-arm.c:19159
msgid "internal_relocation (type: OFFSET_IMM) not fixed up"
msgstr ""
-#: config/tc-arm.c:19188 config/tc-cris.c:3925 config/tc-mcore.c:1926
+#: config/tc-arm.c:19180 config/tc-cris.c:3925 config/tc-mcore.c:1926
#: config/tc-mmix.c:2859 config/tc-ns32k.c:2248 config/tc-score.c:5501
msgid "<unknown>"
msgstr ""
-#: config/tc-arm.c:19191 config/tc-arm.c:19212 config/tc-score.c:5503
+#: config/tc-arm.c:19183 config/tc-arm.c:19204 config/tc-score.c:5503
#, c-format
msgid "cannot represent %s relocation in this object file format"
msgstr ""
-#: config/tc-arm.c:19446
+#: config/tc-arm.c:19438
#, c-format
msgid "%s: unexpected function type: %d"
msgstr ""
-#: config/tc-arm.c:19569
+#: config/tc-arm.c:19561
msgid "use of old and new-style options to set CPU type"
msgstr ""
-#: config/tc-arm.c:19579
+#: config/tc-arm.c:19571
msgid "use of old and new-style options to set FPU type"
msgstr ""
-#: config/tc-arm.c:19654
+#: config/tc-arm.c:19646
msgid "hard-float conflicts with specified fpu"
msgstr ""
-#: config/tc-arm.c:19837
+#: config/tc-arm.c:19829
msgid "generate PIC code"
msgstr ""
-#: config/tc-arm.c:19838
+#: config/tc-arm.c:19830
msgid "assemble Thumb code"
msgstr ""
-#: config/tc-arm.c:19839
+#: config/tc-arm.c:19831
msgid "support ARM/Thumb interworking"
msgstr ""
-#: config/tc-arm.c:19841
+#: config/tc-arm.c:19833
msgid "code uses 32-bit program counter"
msgstr ""
-#: config/tc-arm.c:19842
+#: config/tc-arm.c:19834
msgid "code uses 26-bit program counter"
msgstr ""
-#: config/tc-arm.c:19843
+#: config/tc-arm.c:19835
msgid "floating point args are in fp regs"
msgstr ""
-#: config/tc-arm.c:19845
+#: config/tc-arm.c:19837
msgid "re-entrant code"
msgstr ""
-#: config/tc-arm.c:19846
+#: config/tc-arm.c:19838
msgid "code is ATPCS conformant"
msgstr ""
-#: config/tc-arm.c:19847
+#: config/tc-arm.c:19839
msgid "assemble for big-endian"
msgstr ""
-#: config/tc-arm.c:19848
+#: config/tc-arm.c:19840
msgid "assemble for little-endian"
msgstr ""
#. These are recognized by the assembler, but have no affect on code.
-#: config/tc-arm.c:19852
+#: config/tc-arm.c:19844
msgid "use frame pointer"
msgstr ""
-#: config/tc-arm.c:19853
+#: config/tc-arm.c:19845
msgid "use stack size checking"
msgstr ""
#. DON'T add any new processors to this list -- we want the whole list
#. to go away... Add them to the processors table instead.
-#: config/tc-arm.c:19869 config/tc-arm.c:19870
+#: config/tc-arm.c:19861 config/tc-arm.c:19862
msgid "use -mcpu=arm1"
msgstr ""
-#: config/tc-arm.c:19871 config/tc-arm.c:19872
+#: config/tc-arm.c:19863 config/tc-arm.c:19864
msgid "use -mcpu=arm2"
msgstr ""
-#: config/tc-arm.c:19873 config/tc-arm.c:19874
+#: config/tc-arm.c:19865 config/tc-arm.c:19866
msgid "use -mcpu=arm250"
msgstr ""
-#: config/tc-arm.c:19875 config/tc-arm.c:19876
+#: config/tc-arm.c:19867 config/tc-arm.c:19868
msgid "use -mcpu=arm3"
msgstr ""
-#: config/tc-arm.c:19877 config/tc-arm.c:19878
+#: config/tc-arm.c:19869 config/tc-arm.c:19870
msgid "use -mcpu=arm6"
msgstr ""
-#: config/tc-arm.c:19879 config/tc-arm.c:19880
+#: config/tc-arm.c:19871 config/tc-arm.c:19872
msgid "use -mcpu=arm600"
msgstr ""
-#: config/tc-arm.c:19881 config/tc-arm.c:19882
+#: config/tc-arm.c:19873 config/tc-arm.c:19874
msgid "use -mcpu=arm610"
msgstr ""
-#: config/tc-arm.c:19883 config/tc-arm.c:19884
+#: config/tc-arm.c:19875 config/tc-arm.c:19876
msgid "use -mcpu=arm620"
msgstr ""
-#: config/tc-arm.c:19885 config/tc-arm.c:19886
+#: config/tc-arm.c:19877 config/tc-arm.c:19878
msgid "use -mcpu=arm7"
msgstr ""
-#: config/tc-arm.c:19887 config/tc-arm.c:19888
+#: config/tc-arm.c:19879 config/tc-arm.c:19880
msgid "use -mcpu=arm70"
msgstr ""
-#: config/tc-arm.c:19889 config/tc-arm.c:19890
+#: config/tc-arm.c:19881 config/tc-arm.c:19882
msgid "use -mcpu=arm700"
msgstr ""
-#: config/tc-arm.c:19891 config/tc-arm.c:19892
+#: config/tc-arm.c:19883 config/tc-arm.c:19884
msgid "use -mcpu=arm700i"
msgstr ""
-#: config/tc-arm.c:19893 config/tc-arm.c:19894
+#: config/tc-arm.c:19885 config/tc-arm.c:19886
msgid "use -mcpu=arm710"
msgstr ""
-#: config/tc-arm.c:19895 config/tc-arm.c:19896
+#: config/tc-arm.c:19887 config/tc-arm.c:19888
msgid "use -mcpu=arm710c"
msgstr ""
-#: config/tc-arm.c:19897 config/tc-arm.c:19898
+#: config/tc-arm.c:19889 config/tc-arm.c:19890
msgid "use -mcpu=arm720"
msgstr ""
-#: config/tc-arm.c:19899 config/tc-arm.c:19900
+#: config/tc-arm.c:19891 config/tc-arm.c:19892
msgid "use -mcpu=arm7d"
msgstr ""
-#: config/tc-arm.c:19901 config/tc-arm.c:19902
+#: config/tc-arm.c:19893 config/tc-arm.c:19894
msgid "use -mcpu=arm7di"
msgstr ""
-#: config/tc-arm.c:19903 config/tc-arm.c:19904
+#: config/tc-arm.c:19895 config/tc-arm.c:19896
msgid "use -mcpu=arm7m"
msgstr ""
-#: config/tc-arm.c:19905 config/tc-arm.c:19906
+#: config/tc-arm.c:19897 config/tc-arm.c:19898
msgid "use -mcpu=arm7dm"
msgstr ""
-#: config/tc-arm.c:19907 config/tc-arm.c:19908
+#: config/tc-arm.c:19899 config/tc-arm.c:19900
msgid "use -mcpu=arm7dmi"
msgstr ""
-#: config/tc-arm.c:19909 config/tc-arm.c:19910
+#: config/tc-arm.c:19901 config/tc-arm.c:19902
msgid "use -mcpu=arm7100"
msgstr ""
-#: config/tc-arm.c:19911 config/tc-arm.c:19912
+#: config/tc-arm.c:19903 config/tc-arm.c:19904
msgid "use -mcpu=arm7500"
msgstr ""
-#: config/tc-arm.c:19913 config/tc-arm.c:19914
+#: config/tc-arm.c:19905 config/tc-arm.c:19906
msgid "use -mcpu=arm7500fe"
msgstr ""
-#: config/tc-arm.c:19915 config/tc-arm.c:19916 config/tc-arm.c:19917
-#: config/tc-arm.c:19918
+#: config/tc-arm.c:19907 config/tc-arm.c:19908 config/tc-arm.c:19909
+#: config/tc-arm.c:19910
msgid "use -mcpu=arm7tdmi"
msgstr ""
-#: config/tc-arm.c:19919 config/tc-arm.c:19920
+#: config/tc-arm.c:19911 config/tc-arm.c:19912
msgid "use -mcpu=arm710t"
msgstr ""
-#: config/tc-arm.c:19921 config/tc-arm.c:19922
+#: config/tc-arm.c:19913 config/tc-arm.c:19914
msgid "use -mcpu=arm720t"
msgstr ""
-#: config/tc-arm.c:19923 config/tc-arm.c:19924
+#: config/tc-arm.c:19915 config/tc-arm.c:19916
msgid "use -mcpu=arm740t"
msgstr ""
-#: config/tc-arm.c:19925 config/tc-arm.c:19926
+#: config/tc-arm.c:19917 config/tc-arm.c:19918
msgid "use -mcpu=arm8"
msgstr ""
-#: config/tc-arm.c:19927 config/tc-arm.c:19928
+#: config/tc-arm.c:19919 config/tc-arm.c:19920
msgid "use -mcpu=arm810"
msgstr ""
-#: config/tc-arm.c:19929 config/tc-arm.c:19930
+#: config/tc-arm.c:19921 config/tc-arm.c:19922
msgid "use -mcpu=arm9"
msgstr ""
-#: config/tc-arm.c:19931 config/tc-arm.c:19932
+#: config/tc-arm.c:19923 config/tc-arm.c:19924
msgid "use -mcpu=arm9tdmi"
msgstr ""
-#: config/tc-arm.c:19933 config/tc-arm.c:19934
+#: config/tc-arm.c:19925 config/tc-arm.c:19926
msgid "use -mcpu=arm920"
msgstr ""
-#: config/tc-arm.c:19935 config/tc-arm.c:19936
+#: config/tc-arm.c:19927 config/tc-arm.c:19928
msgid "use -mcpu=arm940"
msgstr ""
-#: config/tc-arm.c:19937
+#: config/tc-arm.c:19929
msgid "use -mcpu=strongarm"
msgstr ""
-#: config/tc-arm.c:19939
+#: config/tc-arm.c:19931
msgid "use -mcpu=strongarm110"
msgstr ""
-#: config/tc-arm.c:19941
+#: config/tc-arm.c:19933
msgid "use -mcpu=strongarm1100"
msgstr ""
-#: config/tc-arm.c:19943
+#: config/tc-arm.c:19935
msgid "use -mcpu=strongarm1110"
msgstr ""
-#: config/tc-arm.c:19944
+#: config/tc-arm.c:19936
msgid "use -mcpu=xscale"
msgstr ""
-#: config/tc-arm.c:19945
+#: config/tc-arm.c:19937
msgid "use -mcpu=iwmmxt"
msgstr ""
-#: config/tc-arm.c:19946
+#: config/tc-arm.c:19938
msgid "use -mcpu=all"
msgstr ""
#. Architecture variants -- don't add any more to this list either.
-#: config/tc-arm.c:19949 config/tc-arm.c:19950
+#: config/tc-arm.c:19941 config/tc-arm.c:19942
msgid "use -march=armv2"
msgstr ""
-#: config/tc-arm.c:19951 config/tc-arm.c:19952
+#: config/tc-arm.c:19943 config/tc-arm.c:19944
msgid "use -march=armv2a"
msgstr ""
-#: config/tc-arm.c:19953 config/tc-arm.c:19954
+#: config/tc-arm.c:19945 config/tc-arm.c:19946
msgid "use -march=armv3"
msgstr ""
-#: config/tc-arm.c:19955 config/tc-arm.c:19956
+#: config/tc-arm.c:19947 config/tc-arm.c:19948
msgid "use -march=armv3m"
msgstr ""
-#: config/tc-arm.c:19957 config/tc-arm.c:19958
+#: config/tc-arm.c:19949 config/tc-arm.c:19950
msgid "use -march=armv4"
msgstr ""
-#: config/tc-arm.c:19959 config/tc-arm.c:19960
+#: config/tc-arm.c:19951 config/tc-arm.c:19952
msgid "use -march=armv4t"
msgstr ""
-#: config/tc-arm.c:19961 config/tc-arm.c:19962
+#: config/tc-arm.c:19953 config/tc-arm.c:19954
msgid "use -march=armv5"
msgstr ""
-#: config/tc-arm.c:19963 config/tc-arm.c:19964
+#: config/tc-arm.c:19955 config/tc-arm.c:19956
msgid "use -march=armv5t"
msgstr ""
-#: config/tc-arm.c:19965 config/tc-arm.c:19966
+#: config/tc-arm.c:19957 config/tc-arm.c:19958
msgid "use -march=armv5te"
msgstr ""
#. Floating point variants -- don't add any more to this list either.
-#: config/tc-arm.c:19969
+#: config/tc-arm.c:19961
msgid "use -mfpu=fpe"
msgstr ""
-#: config/tc-arm.c:19970
+#: config/tc-arm.c:19962
msgid "use -mfpu=fpa10"
msgstr ""
-#: config/tc-arm.c:19971
+#: config/tc-arm.c:19963
msgid "use -mfpu=fpa11"
msgstr ""
-#: config/tc-arm.c:19973
+#: config/tc-arm.c:19965
msgid "use either -mfpu=softfpa or -mfpu=softvfp"
msgstr ""
-#: config/tc-arm.c:20234
+#: config/tc-arm.c:20226
msgid "invalid architectural extension"
msgstr ""
-#: config/tc-arm.c:20248
+#: config/tc-arm.c:20240
msgid "missing architectural extension"
msgstr ""
-#: config/tc-arm.c:20261
+#: config/tc-arm.c:20253
#, c-format
-msgid "unknown architectural extnsion `%s'"
+msgid "unknown architectural extension `%s'"
msgstr ""
-#: config/tc-arm.c:20285
+#: config/tc-arm.c:20277
#, c-format
msgid "missing cpu name `%s'"
msgstr ""
-#: config/tc-arm.c:20310 config/tc-arm.c:20695
+#: config/tc-arm.c:20302 config/tc-arm.c:20687
#, c-format
msgid "unknown cpu `%s'"
msgstr ""
-#: config/tc-arm.c:20328
+#: config/tc-arm.c:20320
#, c-format
msgid "missing architecture name `%s'"
msgstr ""
-#: config/tc-arm.c:20345 config/tc-arm.c:20729 config/tc-arm.c:20760
+#: config/tc-arm.c:20337 config/tc-arm.c:20721 config/tc-arm.c:20752
#, c-format
msgid "unknown architecture `%s'\n"
msgstr ""
-#: config/tc-arm.c:20361 config/tc-arm.c:20791
+#: config/tc-arm.c:20353 config/tc-arm.c:20783
#, c-format
msgid "unknown floating point format `%s'\n"
msgstr ""
-#: config/tc-arm.c:20377
+#: config/tc-arm.c:20369
#, c-format
msgid "unknown floating point abi `%s'\n"
msgstr ""
-#: config/tc-arm.c:20393
+#: config/tc-arm.c:20385
#, c-format
msgid "unknown EABI `%s'\n"
msgstr ""
-#: config/tc-arm.c:20400
+#: config/tc-arm.c:20392
msgid "<cpu name>\t assemble for CPU <cpu name>"
msgstr ""
-#: config/tc-arm.c:20402
+#: config/tc-arm.c:20394
msgid "<arch name>\t assemble for architecture <arch name>"
msgstr ""
-#: config/tc-arm.c:20404
+#: config/tc-arm.c:20396
msgid "<fpu name>\t assemble for FPU architecture <fpu name>"
msgstr ""
-#: config/tc-arm.c:20406
+#: config/tc-arm.c:20398
msgid "<abi>\t assemble for floating point ABI <abi>"
msgstr ""
-#: config/tc-arm.c:20409
+#: config/tc-arm.c:20401
msgid "<ver>\t assemble for eabi version <ver>"
msgstr ""
-#: config/tc-arm.c:20451 config/tc-arm.c:20471 config/tc-arm.c:20493
+#: config/tc-arm.c:20443 config/tc-arm.c:20463 config/tc-arm.c:20485
#, c-format
msgid "option `-%c%s' is deprecated: %s"
msgstr ""
-#: config/tc-arm.c:20514
+#: config/tc-arm.c:20506
#, c-format
msgid " ARM-specific assembler options:\n"
msgstr ""
-#: config/tc-arm.c:20525
+#: config/tc-arm.c:20517
#, c-format
msgid " -EB assemble code for a big-endian cpu\n"
msgstr ""
-#: config/tc-arm.c:20530
+#: config/tc-arm.c:20522
#, c-format
msgid " -EL assemble code for a little-endian cpu\n"
msgstr ""
projects / binutils-gdb.git / commitdiff