radeonsi/gfx9: ELEMENT_SIZE change

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c
index 913a2ddbfe61cb45a2f721d59e045222d62c6ce0..33ebe2e7d97ecee702f69b3d7d43c8d9b71371b0 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -468,16 +468,20 @@ static void setup_scratch_rsrc_user_sgprs(struct si_context *sctx,
        /* Disable address clamping */
        uint32_t scratch_dword2 = 0xffffffff;
        uint32_t scratch_dword3 =
-               S_008F0C_ELEMENT_SIZE(max_private_element_size) |
                S_008F0C_INDEX_STRIDE(3) |
                S_008F0C_ADD_TID_ENABLE(1);
 
+       if (sctx->b.chip_class >= GFX9) {
+               assert(max_private_element_size == 1); /* always 4 bytes on GFX9 */
+       } else {
+               scratch_dword3 |= S_008F0C_ELEMENT_SIZE(max_private_element_size);
 
-       if (sctx->screen->b.chip_class < VI) {
-               /* BUF_DATA_FORMAT is ignored, but it cannot be
-                  BUF_DATA_FORMAT_INVALID. */
-               scratch_dword3 |=
-                       S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8);
+               if (sctx->b.chip_class < VI) {
+                       /* BUF_DATA_FORMAT is ignored, but it cannot be
+                        * BUF_DATA_FORMAT_INVALID. */
+                       scratch_dword3 |=
+                               S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_8);
+               }
        }
 
        radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index c13bc942dc7c94dc985e6817ca2cb67a26b5ae47..71b511c958d74ab693a8602d3c2e923d3dd2d7cd 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -1331,10 +1331,14 @@ void si_set_ring_buffer(struct pipe_context *ctx, uint slot,
                          S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
                          S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
                          S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
-                         S_008F0C_ELEMENT_SIZE(element_size) |
                          S_008F0C_INDEX_STRIDE(index_stride) |
                          S_008F0C_ADD_TID_ENABLE(add_tid);
 
+               if (sctx->b.chip_class >= GFX9)
+                       assert(!swizzle || element_size == 1); /* always 4 bytes on GFX9 */
+               else
+                       desc[3] |= S_008F0C_ELEMENT_SIZE(element_size);
+
                pipe_resource_reference(&buffers->buffers[slot], buffer);
                radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
                                      (struct r600_resource*)buffer,