ilo: replace cmd by dw0 in GPE

With e3c251071b0c9396c3ec76d1cf943c60ae297281, the magic values are gone.  We
no longer need "cmd" to hide them.  Replace it by dw0.

diff --git a/src/gallium/drivers/ilo/ilo_gpe_gen6.h b/src/gallium/drivers/ilo/ilo_gpe_gen6.h
index 47aebbb3cb43f07f6f1d1d0a23fef6580290e5fb..7175bfb55d77bd163021b1e8e08dd63bb6d0729d 100644 (file)
--- a/src/gallium/drivers/ilo/ilo_gpe_gen6.h
+++ b/src/gallium/drivers/ilo/ilo_gpe_gen6.h
@@ -244,17 +244,20 @@ gen6_emit_MI_STORE_DATA_IMM(const struct ilo_dev_info *dev,
                             uint64_t val, bool store_qword,
                             struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_MI_CMD(MI_STORE_DATA_IMM);
    const uint8_t cmd_len = (store_qword) ? 5 : 4;
-   /* must use GGTT on GEN6 as in PIPE_CONTROL */
-   const uint32_t cmd_flags = (dev->gen == ILO_GEN(6)) ? (1 << 22) : 0;
+   uint32_t dw0 = GEN6_MI_CMD(MI_STORE_DATA_IMM) | (cmd_len - 2);
 
    ILO_GPE_VALID_GEN(dev, 6, 7.5);
 
    assert(bo_offset % ((store_qword) ? 8 : 4) == 0);
 
+   /* must use GGTT on GEN6 as in PIPE_CONTROL */
+   if (dev->gen == ILO_GEN(6)) {
+      dw0 |= GEN6_MI_STORE_DATA_IMM_DW0_USE_GGTT;
+   }
+
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | cmd_flags | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, 0);
    ilo_cp_write_bo(cp, bo_offset, bo, INTEL_RELOC_WRITE | INTEL_RELOC_GGTT);
    ilo_cp_write(cp, (uint32_t) val);
@@ -272,15 +275,15 @@ gen6_emit_MI_LOAD_REGISTER_IMM(const struct ilo_dev_info *dev,
                                uint32_t reg, uint32_t val,
                                struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_MI_CMD(MI_LOAD_REGISTER_IMM);
    const uint8_t cmd_len = 3;
+   const uint32_t dw0 = GEN6_MI_CMD(MI_LOAD_REGISTER_IMM) | (cmd_len - 2);
 
    ILO_GPE_VALID_GEN(dev, 6, 7.5);
 
    assert(reg % 4 == 0);
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, reg);
    ilo_cp_write(cp, val);
    ilo_cp_end(cp);
@@ -291,17 +294,20 @@ gen6_emit_MI_STORE_REGISTER_MEM(const struct ilo_dev_info *dev,
                                 struct intel_bo *bo, uint32_t bo_offset,
                                 uint32_t reg, struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_MI_CMD(MI_STORE_REGISTER_MEM);
    const uint8_t cmd_len = 3;
-   /* must use GGTT on GEN6 as in PIPE_CONTROL */
-   const uint32_t cmd_flags = (dev->gen == ILO_GEN(6)) ? (1 << 22) : 0;
+   uint32_t dw0 = GEN6_MI_CMD(MI_STORE_REGISTER_MEM) | (cmd_len - 2);
 
    ILO_GPE_VALID_GEN(dev, 6, 7.5);
 
    assert(reg % 4 == 0 && bo_offset % 4 == 0);
 
+   /* must use GGTT on GEN6 as in PIPE_CONTROL */
+   if (dev->gen == ILO_GEN(6)) {
+      dw0 |= GEN6_MI_STORE_REGISTER_MEM_DW0_USE_GGTT;
+   }
+
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | cmd_flags | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, reg);
    ilo_cp_write_bo(cp, bo_offset, bo, INTEL_RELOC_WRITE | INTEL_RELOC_GGTT);
    ilo_cp_end(cp);
@@ -312,8 +318,8 @@ gen6_emit_MI_REPORT_PERF_COUNT(const struct ilo_dev_info *dev,
                                struct intel_bo *bo, uint32_t bo_offset,
                                uint32_t report_id, struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_MI_CMD(MI_REPORT_PERF_COUNT);
    const uint8_t cmd_len = 3;
+   const uint32_t dw0 = GEN6_MI_CMD(MI_REPORT_PERF_COUNT) | (cmd_len - 2);
 
    ILO_GPE_VALID_GEN(dev, 6, 7.5);
 
@@ -324,7 +330,7 @@ gen6_emit_MI_REPORT_PERF_COUNT(const struct ilo_dev_info *dev,
       bo_offset |= 0x1;
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write_bo(cp, bo_offset, bo, INTEL_RELOC_WRITE | INTEL_RELOC_GGTT);
    ilo_cp_write(cp, report_id);
    ilo_cp_end(cp);
@@ -343,8 +349,9 @@ gen6_emit_STATE_BASE_ADDRESS(const struct ilo_dev_info *dev,
                              uint32_t instruction_size,
                              struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_CMD(COMMON, STATE_BASE_ADDRESS);
    const uint8_t cmd_len = 10;
+   const uint32_t dw0 = GEN6_RENDER_CMD(COMMON, STATE_BASE_ADDRESS) |
+                        (cmd_len - 2);
 
    ILO_GPE_VALID_GEN(dev, 6, 7.5);
 
@@ -353,7 +360,7 @@ gen6_emit_STATE_BASE_ADDRESS(const struct ilo_dev_info *dev,
             indirect_object_size | instruction_size) & 0xfff) == 0);
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
 
    ilo_cp_write_bo(cp, 1, general_state_bo, 0);
    ilo_cp_write_bo(cp, 1, surface_state_bo, 0);
@@ -401,13 +408,13 @@ gen6_emit_STATE_SIP(const struct ilo_dev_info *dev,
                     uint32_t sip,
                     struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_CMD(COMMON, STATE_SIP);
    const uint8_t cmd_len = 2;
+   const uint32_t dw0 = GEN6_RENDER_CMD(COMMON, STATE_SIP) | (cmd_len - 2);
 
    ILO_GPE_VALID_GEN(dev, 6, 7.5);
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, sip);
    ilo_cp_end(cp);
 }
@@ -417,13 +424,14 @@ gen6_emit_3DSTATE_VF_STATISTICS(const struct ilo_dev_info *dev,
                                 bool enable,
                                 struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_CMD(SINGLE_DW, 3DSTATE_VF_STATISTICS);
    const uint8_t cmd_len = 1;
+   const uint32_t dw0 = GEN6_RENDER_CMD(SINGLE_DW, 3DSTATE_VF_STATISTICS) |
+                        enable;
 
    ILO_GPE_VALID_GEN(dev, 6, 7.5);
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | enable);
+   ilo_cp_write(cp, dw0);
    ilo_cp_end(cp);
 }
 
@@ -432,8 +440,9 @@ gen6_emit_PIPELINE_SELECT(const struct ilo_dev_info *dev,
                           int pipeline,
                           struct ilo_cp *cp)
 {
-   const int cmd = GEN6_RENDER_CMD(SINGLE_DW, PIPELINE_SELECT);
    const uint8_t cmd_len = 1;
+   const uint32_t dw0 = GEN6_RENDER_CMD(SINGLE_DW, PIPELINE_SELECT) |
+                        pipeline;
 
    ILO_GPE_VALID_GEN(dev, 6, 7.5);
 
@@ -441,7 +450,7 @@ gen6_emit_PIPELINE_SELECT(const struct ilo_dev_info *dev,
    assert(pipeline == 0x0 || pipeline == 0x1);
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | pipeline);
+   ilo_cp_write(cp, dw0);
    ilo_cp_end(cp);
 }
 
@@ -451,8 +460,9 @@ gen6_emit_MEDIA_VFE_STATE(const struct ilo_dev_info *dev,
                           int urb_entry_size,
                           struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_CMD(MEDIA, MEDIA_VFE_STATE);
    const uint8_t cmd_len = 8;
+   const uint32_t dw0 = GEN6_RENDER_CMD(MEDIA, MEDIA_VFE_STATE) |
+                        (cmd_len - 2);
    uint32_t dw2, dw4;
 
    ILO_GPE_VALID_GEN(dev, 6, 6);
@@ -466,7 +476,7 @@ gen6_emit_MEDIA_VFE_STATE(const struct ilo_dev_info *dev,
          480;                    /* CURBE Allocation Size */
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, 0); /* scratch */
    ilo_cp_write(cp, dw2);
    ilo_cp_write(cp, 0); /* MBZ */
@@ -482,8 +492,9 @@ gen6_emit_MEDIA_CURBE_LOAD(const struct ilo_dev_info *dev,
                           uint32_t buf, int size,
                           struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_CMD(MEDIA, MEDIA_CURBE_LOAD);
    const uint8_t cmd_len = 4;
+   const uint32_t dw0 = GEN6_RENDER_CMD(MEDIA, MEDIA_CURBE_LOAD) |
+                        (cmd_len - 2);
 
    ILO_GPE_VALID_GEN(dev, 6, 6);
 
@@ -492,7 +503,7 @@ gen6_emit_MEDIA_CURBE_LOAD(const struct ilo_dev_info *dev,
    size = align(size, 32);
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, 0); /* MBZ */
    ilo_cp_write(cp, size);
    ilo_cp_write(cp, buf);
@@ -504,16 +515,16 @@ gen6_emit_MEDIA_INTERFACE_DESCRIPTOR_LOAD(const struct ilo_dev_info *dev,
                                           uint32_t offset, int num_ids,
                                           struct ilo_cp *cp)
 {
-   const uint32_t cmd =
-      GEN6_RENDER_CMD(MEDIA, MEDIA_INTERFACE_DESCRIPTOR_LOAD);
    const uint8_t cmd_len = 4;
+   const uint32_t dw0 =
+      GEN6_RENDER_CMD(MEDIA, MEDIA_INTERFACE_DESCRIPTOR_LOAD) | (cmd_len - 2);
 
    ILO_GPE_VALID_GEN(dev, 6, 6);
 
    assert(offset % 32 == 0);
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, 0); /* MBZ */
    /* every ID has 8 DWords */
    ilo_cp_write(cp, num_ids * 8 * 4);
@@ -526,8 +537,9 @@ gen6_emit_MEDIA_GATEWAY_STATE(const struct ilo_dev_info *dev,
                               int id, int byte, int thread_count,
                               struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_CMD(MEDIA, MEDIA_GATEWAY_STATE);
    const uint8_t cmd_len = 2;
+   const uint32_t dw0 = GEN6_RENDER_CMD(MEDIA, MEDIA_GATEWAY_STATE) |
+                        (cmd_len - 2);
    uint32_t dw1;
 
    ILO_GPE_VALID_GEN(dev, 6, 6);
@@ -537,7 +549,7 @@ gen6_emit_MEDIA_GATEWAY_STATE(const struct ilo_dev_info *dev,
          thread_count;
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, dw1);
    ilo_cp_end(cp);
 }
@@ -548,8 +560,9 @@ gen6_emit_MEDIA_STATE_FLUSH(const struct ilo_dev_info *dev,
                             int barrier_mask,
                             struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_CMD(MEDIA, MEDIA_STATE_FLUSH);
    const uint8_t cmd_len = 2;
+   const uint32_t dw0 = GEN6_RENDER_CMD(MEDIA, MEDIA_STATE_FLUSH) |
+                        (cmd_len - 2);
    uint32_t dw1;
 
    ILO_GPE_VALID_GEN(dev, 6, 6);
@@ -558,7 +571,7 @@ gen6_emit_MEDIA_STATE_FLUSH(const struct ilo_dev_info *dev,
          barrier_mask;
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, dw1);
    ilo_cp_end(cp);
 }
@@ -577,16 +590,17 @@ gen6_emit_3DSTATE_BINDING_TABLE_POINTERS(const struct ilo_dev_info *dev,
                                          uint32_t ps_binding_table,
                                          struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_BINDING_TABLE_POINTERS);
    const uint8_t cmd_len = 4;
+   const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_BINDING_TABLE_POINTERS) |
+                        GEN6_PTR_BINDING_TABLE_DW0_VS_CHANGED |
+                        GEN6_PTR_BINDING_TABLE_DW0_GS_CHANGED |
+                        GEN6_PTR_BINDING_TABLE_DW0_PS_CHANGED |
+                        (cmd_len - 2);
 
    ILO_GPE_VALID_GEN(dev, 6, 6);
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2) |
-                    GEN6_PTR_BINDING_TABLE_DW0_VS_CHANGED |
-                    GEN6_PTR_BINDING_TABLE_DW0_GS_CHANGED |
-                    GEN6_PTR_BINDING_TABLE_DW0_PS_CHANGED);
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, vs_binding_table);
    ilo_cp_write(cp, gs_binding_table);
    ilo_cp_write(cp, ps_binding_table);
@@ -600,16 +614,17 @@ gen6_emit_3DSTATE_SAMPLER_STATE_POINTERS(const struct ilo_dev_info *dev,
                                          uint32_t ps_sampler_state,
                                          struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_SAMPLER_STATE_POINTERS);
    const uint8_t cmd_len = 4;
+   const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_SAMPLER_STATE_POINTERS) |
+                        GEN6_PTR_SAMPLER_DW0_VS_CHANGED |
+                        GEN6_PTR_SAMPLER_DW0_GS_CHANGED |
+                        GEN6_PTR_SAMPLER_DW0_PS_CHANGED |
+                        (cmd_len - 2);
 
    ILO_GPE_VALID_GEN(dev, 6, 6);
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2) |
-                    GEN6_PTR_SAMPLER_DW0_VS_CHANGED |
-                    GEN6_PTR_SAMPLER_DW0_GS_CHANGED |
-                    GEN6_PTR_SAMPLER_DW0_PS_CHANGED);
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, vs_sampler_state);
    ilo_cp_write(cp, gs_sampler_state);
    ilo_cp_write(cp, ps_sampler_state);
@@ -622,8 +637,8 @@ gen6_emit_3DSTATE_URB(const struct ilo_dev_info *dev,
                       int vs_entry_size, int gs_entry_size,
                       struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_URB);
    const uint8_t cmd_len = 3;
+   const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_URB) | (cmd_len - 2);
    const int row_size = 128; /* 1024 bits */
    int vs_alloc_size, gs_alloc_size;
    int vs_num_entries, gs_num_entries;
@@ -653,7 +668,7 @@ gen6_emit_3DSTATE_URB(const struct ilo_dev_info *dev,
       gs_num_entries = 256;
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, (vs_alloc_size - 1) << GEN6_URB_DW1_VS_ENTRY_SIZE__SHIFT |
                     vs_num_entries << GEN6_URB_DW1_VS_ENTRY_COUNT__SHIFT);
    ilo_cp_write(cp, gs_num_entries << GEN6_URB_DW2_GS_ENTRY_COUNT__SHIFT |
@@ -667,8 +682,8 @@ gen6_emit_3DSTATE_VERTEX_BUFFERS(const struct ilo_dev_info *dev,
                                  const struct ilo_vb_state *vb,
                                  struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_VERTEX_BUFFERS);
    uint8_t cmd_len;
+   uint32_t dw0;
    unsigned hw_idx;
 
    ILO_GPE_VALID_GEN(dev, 6, 7.5);
@@ -684,9 +699,11 @@ gen6_emit_3DSTATE_VERTEX_BUFFERS(const struct ilo_dev_info *dev,
       return;
 
    cmd_len = 1 + 4 * ve->vb_count;
+   dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_VERTEX_BUFFERS) |
+         (cmd_len - 2);
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
 
    for (hw_idx = 0; hw_idx < ve->vb_count; hw_idx++) {
       const unsigned instance_divisor = ve->instance_divisors[hw_idx];
@@ -803,8 +820,8 @@ gen6_emit_3DSTATE_VERTEX_ELEMENTS(const struct ilo_dev_info *dev,
                                   bool prepend_generated_ids,
                                   struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_VERTEX_ELEMENTS);
    uint8_t cmd_len;
+   uint32_t dw0;
    unsigned i;
 
    ILO_GPE_VALID_GEN(dev, 6, 7.5);
@@ -827,8 +844,11 @@ gen6_emit_3DSTATE_VERTEX_ELEMENTS(const struct ilo_dev_info *dev,
             &dummy);
 
       cmd_len = 3;
+      dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_VERTEX_ELEMENTS) |
+            (cmd_len - 2);
+
       ilo_cp_begin(cp, cmd_len);
-      ilo_cp_write(cp, cmd | (cmd_len - 2));
+      ilo_cp_write(cp, dw0);
       ilo_cp_write_multi(cp, dummy.payload, 2);
       ilo_cp_end(cp);
 
@@ -836,9 +856,11 @@ gen6_emit_3DSTATE_VERTEX_ELEMENTS(const struct ilo_dev_info *dev,
    }
 
    cmd_len = 2 * (ve->count + prepend_generated_ids) + 1;
+   dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_VERTEX_ELEMENTS) |
+         (cmd_len - 2);
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
 
    if (prepend_generated_ids) {
       struct ilo_ve_cso gen_ids;
@@ -877,11 +899,11 @@ gen6_emit_3DSTATE_INDEX_BUFFER(const struct ilo_dev_info *dev,
                                bool enable_cut_index,
                                struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_INDEX_BUFFER);
    const uint8_t cmd_len = 3;
    struct ilo_buffer *buf = ilo_buffer(ib->hw_resource);
    uint32_t start_offset, end_offset;
    int format;
+   uint32_t dw0;
 
    ILO_GPE_VALID_GEN(dev, 6, 7.5);
 
@@ -919,10 +941,14 @@ gen6_emit_3DSTATE_INDEX_BUFFER(const struct ilo_dev_info *dev,
    end_offset -= (end_offset % ib->hw_index_size);
    end_offset--;
 
+   dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_INDEX_BUFFER) |
+         format |
+         (cmd_len - 2);
+   if (enable_cut_index)
+      dw0 |= GEN6_IB_DW0_CUT_INDEX_ENABLE;
+
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2) |
-                    ((enable_cut_index) ? GEN6_IB_DW0_CUT_INDEX_ENABLE : 0) |
-                    format);
+   ilo_cp_write(cp, dw0);
    ilo_cp_write_bo(cp, start_offset, buf->bo, 0);
    ilo_cp_write_bo(cp, end_offset, buf->bo, 0);
    ilo_cp_end(cp);
@@ -935,16 +961,17 @@ gen6_emit_3DSTATE_VIEWPORT_STATE_POINTERS(const struct ilo_dev_info *dev,
                                           uint32_t cc_viewport,
                                           struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_VIEWPORT_STATE_POINTERS);
    const uint8_t cmd_len = 4;
+   const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_VIEWPORT_STATE_POINTERS) |
+                        GEN6_PTR_VP_DW0_CLIP_CHANGED |
+                        GEN6_PTR_VP_DW0_SF_CHANGED |
+                        GEN6_PTR_VP_DW0_CC_CHANGED |
+                        (cmd_len - 2);
 
    ILO_GPE_VALID_GEN(dev, 6, 6);
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2) |
-                    GEN6_PTR_VP_DW0_CLIP_CHANGED |
-                    GEN6_PTR_VP_DW0_SF_CHANGED |
-                    GEN6_PTR_VP_DW0_CC_CHANGED);
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, clip_viewport);
    ilo_cp_write(cp, sf_viewport);
    ilo_cp_write(cp, cc_viewport);
@@ -958,13 +985,14 @@ gen6_emit_3DSTATE_CC_STATE_POINTERS(const struct ilo_dev_info *dev,
                                     uint32_t color_calc_state,
                                     struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_CC_STATE_POINTERS);
    const uint8_t cmd_len = 4;
+   const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_CC_STATE_POINTERS) |
+                        (cmd_len - 2);
 
    ILO_GPE_VALID_GEN(dev, 6, 6);
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, blend_state | 1);
    ilo_cp_write(cp, depth_stencil_state | 1);
    ilo_cp_write(cp, color_calc_state | 1);
@@ -976,13 +1004,14 @@ gen6_emit_3DSTATE_SCISSOR_STATE_POINTERS(const struct ilo_dev_info *dev,
                                          uint32_t scissor_rect,
                                          struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_SCISSOR_STATE_POINTERS);
    const uint8_t cmd_len = 2;
+   const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_SCISSOR_STATE_POINTERS) |
+                        (cmd_len - 2);
 
    ILO_GPE_VALID_GEN(dev, 6, 7.5);
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, scissor_rect);
    ilo_cp_end(cp);
 }
@@ -993,8 +1022,8 @@ gen6_emit_3DSTATE_VS(const struct ilo_dev_info *dev,
                      int num_samplers,
                      struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_VS);
    const uint8_t cmd_len = 6;
+   const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_VS) | (cmd_len - 2);
    const struct ilo_shader_cso *cso;
    uint32_t dw2, dw4, dw5;
 
@@ -1002,7 +1031,7 @@ gen6_emit_3DSTATE_VS(const struct ilo_dev_info *dev,
 
    if (!vs) {
       ilo_cp_begin(cp, cmd_len);
-      ilo_cp_write(cp, cmd | (cmd_len - 2));
+      ilo_cp_write(cp, dw0);
       ilo_cp_write(cp, 0);
       ilo_cp_write(cp, 0);
       ilo_cp_write(cp, 0);
@@ -1020,7 +1049,7 @@ gen6_emit_3DSTATE_VS(const struct ilo_dev_info *dev,
    dw2 |= ((num_samplers + 3) / 4) << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT;
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, ilo_shader_get_kernel_offset(vs));
    ilo_cp_write(cp, dw2);
    ilo_cp_write(cp, 0); /* scratch */
@@ -1036,8 +1065,8 @@ gen6_emit_3DSTATE_GS(const struct ilo_dev_info *dev,
                      int verts_per_prim,
                      struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_GS);
    const uint8_t cmd_len = 7;
+   const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_GS) | (cmd_len - 2);
    uint32_t dw1, dw2, dw4, dw5, dw6;
 
    ILO_GPE_VALID_GEN(dev, 6, 6);
@@ -1088,7 +1117,7 @@ gen6_emit_3DSTATE_GS(const struct ilo_dev_info *dev,
    }
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, dw1);
    ilo_cp_write(cp, dw2);
    ilo_cp_write(cp, 0);
@@ -1106,8 +1135,8 @@ gen6_emit_3DSTATE_CLIP(const struct ilo_dev_info *dev,
                        int num_viewports,
                        struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_CLIP);
    const uint8_t cmd_len = 4;
+   const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_CLIP) | (cmd_len - 2);
    uint32_t dw1, dw2, dw3;
 
    ILO_GPE_VALID_GEN(dev, 6, 7.5);
@@ -1140,7 +1169,7 @@ gen6_emit_3DSTATE_CLIP(const struct ilo_dev_info *dev,
    }
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, dw1);
    ilo_cp_write(cp, dw2);
    ilo_cp_write(cp, dw3);
@@ -1153,8 +1182,8 @@ gen6_emit_3DSTATE_SF(const struct ilo_dev_info *dev,
                      const struct ilo_shader_state *fs,
                      struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_SF);
    const uint8_t cmd_len = 20;
+   const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_SF) | (cmd_len - 2);
    uint32_t payload_raster[6], payload_sbe[13];
 
    ILO_GPE_VALID_GEN(dev, 6, 6);
@@ -1165,7 +1194,7 @@ gen6_emit_3DSTATE_SF(const struct ilo_dev_info *dev,
          fs, payload_sbe, Elements(payload_sbe));
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, payload_sbe[0]);
    ilo_cp_write_multi(cp, payload_raster, 6);
    ilo_cp_write_multi(cp, &payload_sbe[1], 12);
@@ -1181,8 +1210,8 @@ gen6_emit_3DSTATE_WM(const struct ilo_dev_info *dev,
                      uint32_t hiz_op,
                      struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_WM);
    const uint8_t cmd_len = 9;
+   const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_WM) | (cmd_len - 2);
    const int num_samples = 1;
    const struct ilo_shader_cso *fs_cso;
    uint32_t dw2, dw4, dw5, dw6;
@@ -1194,7 +1223,7 @@ gen6_emit_3DSTATE_WM(const struct ilo_dev_info *dev,
       const int max_threads = (dev->gt == 2) ? 80 : 40;
 
       ilo_cp_begin(cp, cmd_len);
-      ilo_cp_write(cp, cmd | (cmd_len - 2));
+      ilo_cp_write(cp, dw0);
       ilo_cp_write(cp, 0);
       ilo_cp_write(cp, 0);
       ilo_cp_write(cp, 0);
@@ -1243,7 +1272,7 @@ gen6_emit_3DSTATE_WM(const struct ilo_dev_info *dev,
    }
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, ilo_shader_get_kernel_offset(fs));
    ilo_cp_write(cp, dw2);
    ilo_cp_write(cp, 0); /* scratch */
@@ -1296,9 +1325,9 @@ gen6_emit_3DSTATE_CONSTANT_VS(const struct ilo_dev_info *dev,
                               int num_bufs,
                               struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_CONSTANT_VS);
    const uint8_t cmd_len = 5;
    uint32_t buf_dw[4], buf_enabled;
+   uint32_t dw0;
 
    ILO_GPE_VALID_GEN(dev, 6, 6);
    assert(num_bufs <= 4);
@@ -1312,8 +1341,12 @@ gen6_emit_3DSTATE_CONSTANT_VS(const struct ilo_dev_info *dev,
    buf_enabled = gen6_fill_3dstate_constant(dev,
          bufs, sizes, num_bufs, 32, buf_dw, Elements(buf_dw));
 
+   dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_CONSTANT_VS) |
+         buf_enabled << 12 |
+         (cmd_len - 2);
+
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2) | buf_enabled << 12);
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, buf_dw[0]);
    ilo_cp_write(cp, buf_dw[1]);
    ilo_cp_write(cp, buf_dw[2]);
@@ -1327,9 +1360,9 @@ gen6_emit_3DSTATE_CONSTANT_GS(const struct ilo_dev_info *dev,
                               int num_bufs,
                               struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_CONSTANT_GS);
    const uint8_t cmd_len = 5;
    uint32_t buf_dw[4], buf_enabled;
+   uint32_t dw0;
 
    ILO_GPE_VALID_GEN(dev, 6, 6);
    assert(num_bufs <= 4);
@@ -1343,8 +1376,12 @@ gen6_emit_3DSTATE_CONSTANT_GS(const struct ilo_dev_info *dev,
    buf_enabled = gen6_fill_3dstate_constant(dev,
          bufs, sizes, num_bufs, 64, buf_dw, Elements(buf_dw));
 
+   dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_CONSTANT_GS) |
+         buf_enabled << 12 |
+         (cmd_len - 2);
+
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2) | buf_enabled << 12);
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, buf_dw[0]);
    ilo_cp_write(cp, buf_dw[1]);
    ilo_cp_write(cp, buf_dw[2]);
@@ -1358,9 +1395,9 @@ gen6_emit_3DSTATE_CONSTANT_PS(const struct ilo_dev_info *dev,
                               int num_bufs,
                               struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_CONSTANT_PS);
    const uint8_t cmd_len = 5;
    uint32_t buf_dw[4], buf_enabled;
+   uint32_t dw0;
 
    ILO_GPE_VALID_GEN(dev, 6, 6);
    assert(num_bufs <= 4);
@@ -1374,8 +1411,12 @@ gen6_emit_3DSTATE_CONSTANT_PS(const struct ilo_dev_info *dev,
    buf_enabled = gen6_fill_3dstate_constant(dev,
          bufs, sizes, num_bufs, 64, buf_dw, Elements(buf_dw));
 
+   dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_CONSTANT_PS) |
+         buf_enabled << 12 |
+         (cmd_len - 2);
+
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2) | buf_enabled << 12);
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, buf_dw[0]);
    ilo_cp_write(cp, buf_dw[1]);
    ilo_cp_write(cp, buf_dw[2]);
@@ -1388,8 +1429,9 @@ gen6_emit_3DSTATE_SAMPLE_MASK(const struct ilo_dev_info *dev,
                               unsigned sample_mask,
                               struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_SAMPLE_MASK);
    const uint8_t cmd_len = 2;
+   const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_SAMPLE_MASK) |
+                        (cmd_len - 2);
    const unsigned valid_mask = 0xf;
 
    ILO_GPE_VALID_GEN(dev, 6, 6);
@@ -1397,7 +1439,7 @@ gen6_emit_3DSTATE_SAMPLE_MASK(const struct ilo_dev_info *dev,
    sample_mask &= valid_mask;
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, sample_mask);
    ilo_cp_end(cp);
 }
@@ -1408,8 +1450,9 @@ gen6_emit_3DSTATE_DRAWING_RECTANGLE(const struct ilo_dev_info *dev,
                                     unsigned width, unsigned height,
                                     struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_DRAWING_RECTANGLE);
    const uint8_t cmd_len = 4;
+   const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_DRAWING_RECTANGLE) |
+                        (cmd_len - 2);
    unsigned xmax = x + width - 1;
    unsigned ymax = y + height - 1;
    int rect_limit;
@@ -1437,7 +1480,7 @@ gen6_emit_3DSTATE_DRAWING_RECTANGLE(const struct ilo_dev_info *dev,
    if (ymax > rect_limit) ymax = rect_limit;
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, y << 16 | x);
    ilo_cp_write(cp, ymax << 16 | xmax);
 
@@ -1490,15 +1533,18 @@ gen6_emit_3DSTATE_DEPTH_BUFFER(const struct ilo_dev_info *dev,
                                const struct ilo_zs_surface *zs,
                                struct ilo_cp *cp)
 {
-   const uint32_t cmd = (dev->gen >= ILO_GEN(7)) ?
-      GEN7_RENDER_CMD(3D, 3DSTATE_DEPTH_BUFFER) :
-      GEN6_RENDER_CMD(3D, 3DSTATE_DEPTH_BUFFER);
    const uint8_t cmd_len = 7;
+   uint32_t dw0;
 
    ILO_GPE_VALID_GEN(dev, 6, 7.5);
 
+   dw0 = (dev->gen >= ILO_GEN(7)) ?
+      GEN7_RENDER_CMD(3D, 3DSTATE_DEPTH_BUFFER) :
+      GEN6_RENDER_CMD(3D, 3DSTATE_DEPTH_BUFFER);
+   dw0 |= (cmd_len - 2);
+
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, zs->payload[0]);
    ilo_cp_write_bo(cp, zs->payload[1], zs->bo, INTEL_RELOC_WRITE);
    ilo_cp_write(cp, zs->payload[2]);
@@ -1513,15 +1559,16 @@ gen6_emit_3DSTATE_POLY_STIPPLE_OFFSET(const struct ilo_dev_info *dev,
                                       int x_offset, int y_offset,
                                       struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_POLY_STIPPLE_OFFSET);
    const uint8_t cmd_len = 2;
+   const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_POLY_STIPPLE_OFFSET) |
+                        (cmd_len - 2);
 
    ILO_GPE_VALID_GEN(dev, 6, 7.5);
    assert(x_offset >= 0 && x_offset <= 31);
    assert(y_offset >= 0 && y_offset <= 31);
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, x_offset << 8 | y_offset);
    ilo_cp_end(cp);
 }
@@ -1531,15 +1578,16 @@ gen6_emit_3DSTATE_POLY_STIPPLE_PATTERN(const struct ilo_dev_info *dev,
                                        const struct pipe_poly_stipple *pattern,
                                        struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_POLY_STIPPLE_PATTERN);
    const uint8_t cmd_len = 33;
+   const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_POLY_STIPPLE_PATTERN) |
+                        (cmd_len - 2);
    int i;
 
    ILO_GPE_VALID_GEN(dev, 6, 7.5);
    assert(Elements(pattern->stipple) == 32);
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    for (i = 0; i < 32; i++)
       ilo_cp_write(cp, pattern->stipple[i]);
    ilo_cp_end(cp);
@@ -1550,8 +1598,9 @@ gen6_emit_3DSTATE_LINE_STIPPLE(const struct ilo_dev_info *dev,
                                unsigned pattern, unsigned factor,
                                struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_LINE_STIPPLE);
    const uint8_t cmd_len = 3;
+   const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_LINE_STIPPLE) |
+                        (cmd_len - 2);
    unsigned inverse;
 
    ILO_GPE_VALID_GEN(dev, 6, 7.5);
@@ -1559,7 +1608,7 @@ gen6_emit_3DSTATE_LINE_STIPPLE(const struct ilo_dev_info *dev,
    assert(factor >= 1 && factor <= 256);
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, pattern);
 
    if (dev->gen >= ILO_GEN(7)) {
@@ -1580,13 +1629,14 @@ static inline void
 gen6_emit_3DSTATE_AA_LINE_PARAMETERS(const struct ilo_dev_info *dev,
                                      struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_AA_LINE_PARAMETERS);
    const uint8_t cmd_len = 3;
+   const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_AA_LINE_PARAMETERS) |
+                        (cmd_len - 2);
 
    ILO_GPE_VALID_GEN(dev, 6, 7.5);
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, 0 << 16 | 0);
    ilo_cp_write(cp, 0 << 16 | 0);
    ilo_cp_end(cp);
@@ -1599,8 +1649,9 @@ gen6_emit_3DSTATE_GS_SVB_INDEX(const struct ilo_dev_info *dev,
                                bool load_vertex_count,
                                struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_GS_SVB_INDEX);
    const uint8_t cmd_len = 4;
+   const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_GS_SVB_INDEX) |
+                        (cmd_len - 2);
    uint32_t dw1;
 
    ILO_GPE_VALID_GEN(dev, 6, 6);
@@ -1611,7 +1662,7 @@ gen6_emit_3DSTATE_GS_SVB_INDEX(const struct ilo_dev_info *dev,
       dw1 |= GEN6_SVBI_DW1_LOAD_INTERNAL_VERTEX_COUNT;
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, dw1);
    ilo_cp_write(cp, svbi);
    ilo_cp_write(cp, max_svbi);
@@ -1625,8 +1676,9 @@ gen6_emit_3DSTATE_MULTISAMPLE(const struct ilo_dev_info *dev,
                               bool pixel_location_center,
                               struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_MULTISAMPLE);
    const uint8_t cmd_len = (dev->gen >= ILO_GEN(7)) ? 4 : 3;
+   const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_MULTISAMPLE) |
+                        (cmd_len - 2);
    uint32_t dw1, dw2, dw3;
 
    ILO_GPE_VALID_GEN(dev, 6, 7.5);
@@ -1661,7 +1713,7 @@ gen6_emit_3DSTATE_MULTISAMPLE(const struct ilo_dev_info *dev,
    }
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, dw1);
    ilo_cp_write(cp, dw2);
    if (dev->gen >= ILO_GEN(7))
@@ -1674,15 +1726,18 @@ gen6_emit_3DSTATE_STENCIL_BUFFER(const struct ilo_dev_info *dev,
                                  const struct ilo_zs_surface *zs,
                                  struct ilo_cp *cp)
 {
-   const uint32_t cmd = (dev->gen >= ILO_GEN(7)) ?
-      GEN7_RENDER_CMD(3D, 3DSTATE_STENCIL_BUFFER) :
-      GEN6_RENDER_CMD(3D, 3DSTATE_STENCIL_BUFFER);
    const uint8_t cmd_len = 3;
+   uint32_t dw0;
 
    ILO_GPE_VALID_GEN(dev, 6, 7.5);
 
+   dw0 = (dev->gen >= ILO_GEN(7)) ?
+      GEN7_RENDER_CMD(3D, 3DSTATE_STENCIL_BUFFER) :
+      GEN6_RENDER_CMD(3D, 3DSTATE_STENCIL_BUFFER);
+   dw0 |= (cmd_len - 2);
+
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    /* see ilo_gpe_init_zs_surface() */
    ilo_cp_write(cp, zs->payload[6]);
    ilo_cp_write_bo(cp, zs->payload[7], zs->separate_s8_bo, INTEL_RELOC_WRITE);
@@ -1694,15 +1749,18 @@ gen6_emit_3DSTATE_HIER_DEPTH_BUFFER(const struct ilo_dev_info *dev,
                                     const struct ilo_zs_surface *zs,
                                     struct ilo_cp *cp)
 {
-   const uint32_t cmd = (dev->gen >= ILO_GEN(7)) ?
-      GEN7_RENDER_CMD(3D, 3DSTATE_HIER_DEPTH_BUFFER) :
-      GEN6_RENDER_CMD(3D, 3DSTATE_HIER_DEPTH_BUFFER);
    const uint8_t cmd_len = 3;
+   uint32_t dw0;
 
    ILO_GPE_VALID_GEN(dev, 6, 7.5);
 
+   dw0 = (dev->gen >= ILO_GEN(7)) ?
+      GEN7_RENDER_CMD(3D, 3DSTATE_HIER_DEPTH_BUFFER) :
+      GEN6_RENDER_CMD(3D, 3DSTATE_HIER_DEPTH_BUFFER);
+   dw0 |= (cmd_len - 2);
+
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    /* see ilo_gpe_init_zs_surface() */
    ilo_cp_write(cp, zs->payload[8]);
    ilo_cp_write_bo(cp, zs->payload[9], zs->hiz_bo, INTEL_RELOC_WRITE);
@@ -1714,14 +1772,15 @@ gen6_emit_3DSTATE_CLEAR_PARAMS(const struct ilo_dev_info *dev,
                                uint32_t clear_val,
                                struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_CLEAR_PARAMS);
    const uint8_t cmd_len = 2;
+   const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_CLEAR_PARAMS) |
+                        GEN6_CLEAR_PARAMS_DW0_VALID |
+                        (cmd_len - 2);
 
    ILO_GPE_VALID_GEN(dev, 6, 6);
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2) |
-                    GEN6_CLEAR_PARAMS_DW0_VALID);
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, clear_val);
    ilo_cp_end(cp);
 }
@@ -1733,8 +1792,8 @@ gen6_emit_PIPE_CONTROL(const struct ilo_dev_info *dev,
                        bool write_qword,
                        struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_CMD(3D, PIPE_CONTROL);
    const uint8_t cmd_len = (write_qword) ? 5 : 4;
+   const uint32_t dw0 = GEN6_RENDER_CMD(3D, PIPE_CONTROL) | (cmd_len - 2);
 
    ILO_GPE_VALID_GEN(dev, 6, 7.5);
 
@@ -1805,7 +1864,7 @@ gen6_emit_PIPE_CONTROL(const struct ilo_dev_info *dev,
       bo_offset |= GEN6_PIPE_CONTROL_DW2_USE_GGTT;
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, dw1);
    ilo_cp_write_bo(cp, bo_offset, bo, INTEL_RELOC_WRITE | INTEL_RELOC_GGTT);
    ilo_cp_write(cp, 0);
@@ -1821,7 +1880,6 @@ gen6_emit_3DPRIMITIVE(const struct ilo_dev_info *dev,
                       bool rectlist,
                       struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DPRIMITIVE);
    const uint8_t cmd_len = 6;
    const int prim = (rectlist) ?
       GEN6_3DPRIM_RECTLIST : ilo_gpe_gen6_translate_pipe_prim(info->mode);
@@ -1829,13 +1887,17 @@ gen6_emit_3DPRIMITIVE(const struct ilo_dev_info *dev,
       GEN6_3DPRIM_DW0_ACCESS_RANDOM : GEN6_3DPRIM_DW0_ACCESS_SEQUENTIAL;
    const uint32_t vb_start = info->start +
       ((info->indexed) ? ib->draw_start_offset : 0);
+   uint32_t dw0;
 
    ILO_GPE_VALID_GEN(dev, 6, 6);
 
+   dw0 = GEN6_RENDER_CMD(3D, 3DPRIMITIVE) |
+         vb_access |
+         prim << GEN6_3DPRIM_DW0_TYPE__SHIFT |
+         (cmd_len - 2);
+
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2) |
-                    prim << GEN6_3DPRIM_DW0_TYPE__SHIFT |
-                    vb_access);
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, info->count);
    ilo_cp_write(cp, vb_start);
    ilo_cp_write(cp, info->instance_count);

diff --git a/src/gallium/drivers/ilo/ilo_gpe_gen7.h b/src/gallium/drivers/ilo/ilo_gpe_gen7.h
index ab9d9e52b167fcd5e2b72cee0b23d974a78fb01b..ca3057582f2801b8d4c0cd865b030e3969786a99 100644 (file)
--- a/src/gallium/drivers/ilo/ilo_gpe_gen7.h
+++ b/src/gallium/drivers/ilo/ilo_gpe_gen7.h
@@ -48,13 +48,14 @@ gen7_emit_3DSTATE_CLEAR_PARAMS(const struct ilo_dev_info *dev,
                                uint32_t clear_val,
                                struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN7_RENDER_CMD(3D, 3DSTATE_CLEAR_PARAMS);
    const uint8_t cmd_len = 3;
+   const uint32_t dw0 = GEN7_RENDER_CMD(3D, 3DSTATE_CLEAR_PARAMS) |
+                        (cmd_len - 2);
 
    ILO_GPE_VALID_GEN(dev, 7, 7.5);
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, clear_val);
    ilo_cp_write(cp, 1);
    ilo_cp_end(cp);
@@ -66,14 +67,16 @@ gen7_emit_3DSTATE_VF(const struct ilo_dev_info *dev,
                      uint32_t cut_index,
                      struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN75_RENDER_CMD(3D, 3DSTATE_VF);
    const uint8_t cmd_len = 2;
+   uint32_t dw0 = GEN75_RENDER_CMD(3D, 3DSTATE_VF) | (cmd_len - 2);
 
    ILO_GPE_VALID_GEN(dev, 7.5, 7.5);
 
+   if (enable_cut_index)
+      dw0 |= GEN75_VF_DW0_CUT_INDEX_ENABLE;
+
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2) |
-                    ((enable_cut_index) ? GEN75_VF_DW0_CUT_INDEX_ENABLE : 0));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, cut_index);
    ilo_cp_end(cp);
 }
@@ -83,15 +86,15 @@ gen7_emit_3dstate_pointer(const struct ilo_dev_info *dev,
                           int subop, uint32_t pointer,
                           struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_TYPE_RENDER |
-                        GEN6_RENDER_SUBTYPE_3D |
-                        subop;
    const uint8_t cmd_len = 2;
+   const uint32_t dw0 = GEN6_RENDER_TYPE_RENDER |
+                        GEN6_RENDER_SUBTYPE_3D |
+                        subop | (cmd_len - 2);
 
    ILO_GPE_VALID_GEN(dev, 7, 7.5);
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, pointer);
    ilo_cp_end(cp);
 }
@@ -111,8 +114,8 @@ gen7_emit_3DSTATE_GS(const struct ilo_dev_info *dev,
                      int num_samplers,
                      struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_GS);
    const uint8_t cmd_len = 7;
+   const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_GS) | (cmd_len - 2);
    const struct ilo_shader_cso *cso;
    uint32_t dw2, dw4, dw5;
 
@@ -120,7 +123,7 @@ gen7_emit_3DSTATE_GS(const struct ilo_dev_info *dev,
 
    if (!gs) {
       ilo_cp_begin(cp, cmd_len);
-      ilo_cp_write(cp, cmd | (cmd_len - 2));
+      ilo_cp_write(cp, dw0);
       ilo_cp_write(cp, 0);
       ilo_cp_write(cp, 0);
       ilo_cp_write(cp, 0);
@@ -139,7 +142,7 @@ gen7_emit_3DSTATE_GS(const struct ilo_dev_info *dev,
    dw2 |= ((num_samplers + 3) / 4) << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT;
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, ilo_shader_get_kernel_offset(gs));
    ilo_cp_write(cp, dw2);
    ilo_cp_write(cp, 0); /* scratch */
@@ -155,8 +158,8 @@ gen7_emit_3DSTATE_SF(const struct ilo_dev_info *dev,
                      enum pipe_format zs_format,
                      struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_SF);
    const uint8_t cmd_len = 7;
+   const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_SF) | (cmd_len - 2);
    const int num_samples = 1;
    uint32_t payload[6];
 
@@ -167,7 +170,7 @@ gen7_emit_3DSTATE_SF(const struct ilo_dev_info *dev,
          payload, Elements(payload));
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write_multi(cp, payload, 6);
    ilo_cp_end(cp);
 }
@@ -179,8 +182,8 @@ gen7_emit_3DSTATE_WM(const struct ilo_dev_info *dev,
                      bool cc_may_kill, uint32_t hiz_op,
                      struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_WM);
    const uint8_t cmd_len = 3;
+   const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_WM) | (cmd_len - 2);
    const int num_samples = 1;
    uint32_t dw1, dw2;
 
@@ -214,7 +217,7 @@ gen7_emit_3DSTATE_WM(const struct ilo_dev_info *dev,
    }
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, dw1);
    ilo_cp_write(cp, dw2);
    ilo_cp_end(cp);
@@ -227,10 +230,10 @@ gen7_emit_3dstate_constant(const struct ilo_dev_info *dev,
                            int num_bufs,
                            struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_TYPE_RENDER |
-                        GEN6_RENDER_SUBTYPE_3D |
-                        subop;
    const uint8_t cmd_len = 7;
+   const uint32_t dw0 = GEN6_RENDER_TYPE_RENDER |
+                        GEN6_RENDER_SUBTYPE_3D |
+                        subop | (cmd_len - 2);
    uint32_t dw[6];
    int total_read_length, i;
 
@@ -287,7 +290,7 @@ gen7_emit_3dstate_constant(const struct ilo_dev_info *dev,
    assert(total_read_length <= 64);
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write_multi(cp, dw, 6);
    ilo_cp_end(cp);
 }
@@ -328,9 +331,10 @@ gen7_emit_3DSTATE_SAMPLE_MASK(const struct ilo_dev_info *dev,
                               int num_samples,
                               struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DSTATE_SAMPLE_MASK);
    const uint8_t cmd_len = 2;
    const unsigned valid_mask = ((1 << num_samples) - 1) | 0x1;
+   const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_SAMPLE_MASK) |
+                        (cmd_len - 2);
 
    ILO_GPE_VALID_GEN(dev, 7, 7.5);
 
@@ -346,7 +350,7 @@ gen7_emit_3DSTATE_SAMPLE_MASK(const struct ilo_dev_info *dev,
    sample_mask &= valid_mask;
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, sample_mask);
    ilo_cp_end(cp);
 }
@@ -377,15 +381,15 @@ gen7_emit_3DSTATE_HS(const struct ilo_dev_info *dev,
                      int num_samplers,
                      struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN7_RENDER_CMD(3D, 3DSTATE_HS);
    const uint8_t cmd_len = 7;
+   const uint32_t dw0 = GEN7_RENDER_CMD(3D, 3DSTATE_HS) | (cmd_len - 2);
 
    ILO_GPE_VALID_GEN(dev, 7, 7.5);
 
    assert(!hs);
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, 0);
    ilo_cp_write(cp, 0);
    ilo_cp_write(cp, 0);
@@ -399,13 +403,13 @@ static inline void
 gen7_emit_3DSTATE_TE(const struct ilo_dev_info *dev,
                      struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN7_RENDER_CMD(3D, 3DSTATE_TE);
    const uint8_t cmd_len = 4;
+   const uint32_t dw0 = GEN7_RENDER_CMD(3D, 3DSTATE_TE) | (cmd_len - 2);
 
    ILO_GPE_VALID_GEN(dev, 7, 7.5);
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, 0);
    ilo_cp_write(cp, 0);
    ilo_cp_write(cp, 0);
@@ -418,15 +422,15 @@ gen7_emit_3DSTATE_DS(const struct ilo_dev_info *dev,
                      int num_samplers,
                      struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN7_RENDER_CMD(3D, 3DSTATE_DS);
    const uint8_t cmd_len = 6;
+   const uint32_t dw0 = GEN7_RENDER_CMD(3D, 3DSTATE_DS) | (cmd_len - 2);
 
    ILO_GPE_VALID_GEN(dev, 7, 7.5);
 
    assert(!ds);
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, 0);
    ilo_cp_write(cp, 0);
    ilo_cp_write(cp, 0);
@@ -443,9 +447,10 @@ gen7_emit_3DSTATE_STREAMOUT(const struct ilo_dev_info *dev,
                             bool rasterizer_discard,
                             struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN7_RENDER_CMD(3D, 3DSTATE_STREAMOUT);
    const uint8_t cmd_len = 3;
    const bool enable = (buffer_mask != 0);
+   const uint32_t dw0 = GEN7_RENDER_CMD(3D, 3DSTATE_STREAMOUT) |
+                        (cmd_len - 2);
    uint32_t dw1, dw2;
    int read_len;
 
@@ -459,7 +464,7 @@ gen7_emit_3DSTATE_STREAMOUT(const struct ilo_dev_info *dev,
       dw2 = 0;
 
       ilo_cp_begin(cp, cmd_len);
-      ilo_cp_write(cp, cmd | (cmd_len - 2));
+      ilo_cp_write(cp, dw0);
       ilo_cp_write(cp, dw1);
       ilo_cp_write(cp, dw2);
       ilo_cp_end(cp);
@@ -492,7 +497,7 @@ gen7_emit_3DSTATE_STREAMOUT(const struct ilo_dev_info *dev,
          (read_len - 1) << GEN7_SO_DW2_STREAM0_READ_LEN__SHIFT;
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, dw1);
    ilo_cp_write(cp, dw2);
    ilo_cp_end(cp);
@@ -504,8 +509,8 @@ gen7_emit_3DSTATE_SBE(const struct ilo_dev_info *dev,
                       const struct ilo_shader_state *fs,
                       struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN7_RENDER_CMD(3D, 3DSTATE_SBE);
    const uint8_t cmd_len = 14;
+   const uint32_t dw0 = GEN7_RENDER_CMD(3D, 3DSTATE_SBE) | (cmd_len - 2);
    uint32_t dw[13];
 
    ILO_GPE_VALID_GEN(dev, 7, 7.5);
@@ -513,7 +518,7 @@ gen7_emit_3DSTATE_SBE(const struct ilo_dev_info *dev,
    ilo_gpe_gen6_fill_3dstate_sf_sbe(dev, rasterizer, fs, dw, Elements(dw));
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write_multi(cp, dw, 13);
    ilo_cp_end(cp);
 }
@@ -524,8 +529,8 @@ gen7_emit_3DSTATE_PS(const struct ilo_dev_info *dev,
                      int num_samplers, bool dual_blend,
                      struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN7_RENDER_CMD(3D, 3DSTATE_PS);
    const uint8_t cmd_len = 8;
+   const uint32_t dw0 = GEN7_RENDER_CMD(3D, 3DSTATE_PS) | (cmd_len - 2);
    const struct ilo_shader_cso *cso;
    uint32_t dw2, dw4, dw5;
 
@@ -551,7 +556,7 @@ gen7_emit_3DSTATE_PS(const struct ilo_dev_info *dev,
       }
 
       ilo_cp_begin(cp, cmd_len);
-      ilo_cp_write(cp, cmd | (cmd_len - 2));
+      ilo_cp_write(cp, dw0);
       ilo_cp_write(cp, 0);
       ilo_cp_write(cp, 0);
       ilo_cp_write(cp, 0);
@@ -575,7 +580,7 @@ gen7_emit_3DSTATE_PS(const struct ilo_dev_info *dev,
       dw4 |= GEN7_PS_DW4_DUAL_SOURCE_BLEND;
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, ilo_shader_get_kernel_offset(fs));
    ilo_cp_write(cp, dw2);
    ilo_cp_write(cp, 0); /* scratch */
@@ -732,10 +737,10 @@ gen7_emit_3dstate_urb(const struct ilo_dev_info *dev,
                       int entry_size,
                       struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_TYPE_RENDER |
-                        GEN6_RENDER_SUBTYPE_3D |
-                        subop;
    const uint8_t cmd_len = 2;
+   const uint32_t dw0 = GEN6_RENDER_TYPE_RENDER |
+                        GEN6_RENDER_SUBTYPE_3D |
+                        subop | (cmd_len - 2);
    const int row_size = 64; /* 512 bits */
    int alloc_size, num_entries, min_entries, max_entries;
 
@@ -813,7 +818,7 @@ gen7_emit_3dstate_urb(const struct ilo_dev_info *dev,
    }
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, offset << GEN7_URB_ANY_DW1_OFFSET__SHIFT |
                     (alloc_size - 1) << GEN7_URB_ANY_DW1_ENTRY_SIZE__SHIFT |
                     num_entries);
@@ -861,10 +866,10 @@ gen7_emit_3dstate_push_constant_alloc(const struct ilo_dev_info *dev,
                                       int subop, int offset, int size,
                                       struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_TYPE_RENDER |
-                        GEN6_RENDER_SUBTYPE_3D |
-                        subop;
    const uint8_t cmd_len = 2;
+   const uint32_t dw0 = GEN6_RENDER_TYPE_RENDER |
+                        GEN6_RENDER_SUBTYPE_3D |
+                        subop | (cmd_len - 2);
    int end;
 
    ILO_GPE_VALID_GEN(dev, 7, 7.5);
@@ -912,7 +917,7 @@ gen7_emit_3dstate_push_constant_alloc(const struct ilo_dev_info *dev,
    }
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, offset << GEN7_PCB_ALLOC_ANY_DW1_OFFSET__SHIFT |
                     size);
    ilo_cp_end(cp);
@@ -968,8 +973,8 @@ gen7_emit_3DSTATE_SO_DECL_LIST(const struct ilo_dev_info *dev,
                                const struct pipe_stream_output_info *so_info,
                                struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN7_RENDER_CMD(3D, 3DSTATE_SO_DECL_LIST);
    uint16_t cmd_len;
+   uint32_t dw0;
    int buffer_selects, num_entries, i;
    uint16_t so_decls[128];
 
@@ -1030,9 +1035,10 @@ gen7_emit_3DSTATE_SO_DECL_LIST(const struct ilo_dev_info *dev,
     * of cmd_len is thus uint16_t.
     */
    cmd_len = 2 * 128 + 3;
+   dw0 = GEN7_RENDER_CMD(3D, 3DSTATE_SO_DECL_LIST) | (cmd_len - 2);
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, 0 << GEN7_SO_DECL_DW1_STREAM3_BUFFER_SELECTS__SHIFT |
                     0 << GEN7_SO_DECL_DW1_STREAM2_BUFFER_SELECTS__SHIFT |
                     0 << GEN7_SO_DECL_DW1_STREAM1_BUFFER_SELECTS__SHIFT |
@@ -1060,8 +1066,9 @@ gen7_emit_3DSTATE_SO_BUFFER(const struct ilo_dev_info *dev,
                             const struct pipe_stream_output_target *so_target,
                             struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN7_RENDER_CMD(3D, 3DSTATE_SO_BUFFER);
    const uint8_t cmd_len = 4;
+   const uint32_t dw0 = GEN7_RENDER_CMD(3D, 3DSTATE_SO_BUFFER) |
+                        (cmd_len - 2);
    struct ilo_buffer *buf;
    int end;
 
@@ -1069,7 +1076,7 @@ gen7_emit_3DSTATE_SO_BUFFER(const struct ilo_dev_info *dev,
 
    if (!so_target || !so_target->buffer) {
       ilo_cp_begin(cp, cmd_len);
-      ilo_cp_write(cp, cmd | (cmd_len - 2));
+      ilo_cp_write(cp, dw0);
       ilo_cp_write(cp, index << GEN7_SO_BUF_DW1_INDEX__SHIFT);
       ilo_cp_write(cp, 0);
       ilo_cp_write(cp, 0);
@@ -1088,7 +1095,7 @@ gen7_emit_3DSTATE_SO_BUFFER(const struct ilo_dev_info *dev,
    end = (base + so_target->buffer_size) & ~3;
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, index << GEN7_SO_BUF_DW1_INDEX__SHIFT |
                     stride);
    ilo_cp_write_bo(cp, base, buf->bo, INTEL_RELOC_WRITE);
@@ -1103,8 +1110,8 @@ gen7_emit_3DPRIMITIVE(const struct ilo_dev_info *dev,
                       bool rectlist,
                       struct ilo_cp *cp)
 {
-   const uint32_t cmd = GEN6_RENDER_CMD(3D, 3DPRIMITIVE);
    const uint8_t cmd_len = 7;
+   const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DPRIMITIVE) | (cmd_len - 2);
    const int prim = (rectlist) ?
       GEN6_3DPRIM_RECTLIST : ilo_gpe_gen6_translate_pipe_prim(info->mode);
    const int vb_access = (info->indexed) ?
@@ -1116,7 +1123,7 @@ gen7_emit_3DPRIMITIVE(const struct ilo_dev_info *dev,
    ILO_GPE_VALID_GEN(dev, 7, 7.5);
 
    ilo_cp_begin(cp, cmd_len);
-   ilo_cp_write(cp, cmd | (cmd_len - 2));
+   ilo_cp_write(cp, dw0);
    ilo_cp_write(cp, vb_access | prim);
    ilo_cp_write(cp, info->count);
    ilo_cp_write(cp, vb_start);