ARM: Add comment about the organization of the IT state register

diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index aa3f47419efe8ef402a836a892a108ecde248847..2bb1cdb15dbecedfe20377de20b2fe6596b238fe 100644 (file)
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -262,6 +262,12 @@ namespace ArmISA
     EndBitUnion(CPSR)
 
     BitUnion8(ITSTATE)
+        /* Note that the split (cond, mask) below is not as in ARM ARM.
+         * But it is more convenient for simulation. The condition
+         * is always the concatenation of the top 3 bits and the next bit,
+         * which applies when one of the bottom 4 bits is set.
+         * Refer to predecoder.cc for the use case.
+         */
         Bitfield<7, 4> cond;
         Bitfield<3, 0> mask;
         // Bitfields for moving to/from CPSR