rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
rstate->placement[3] = RADEON_GEM_DOMAIN_GTT;
- pitch = (tmp->pitch[0] / tmp->bpt);
- pitch = (pitch + 0x7) & ~0x7;
+ pitch = align(tmp->pitch[0] / tmp->bpt, 8);
/* FIXME properly handle first level != 0 */
rstate->states[EG_PS_RESOURCE__RESOURCE0_WORD0] =
rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
rstate->placement[3] = RADEON_GEM_DOMAIN_GTT;
- pitch = (tmp->pitch[0] / tmp->bpt);
- pitch = (pitch + 0x7) & ~0x7;
+ pitch = align(tmp->pitch[0] / tmp->bpt, 8);
/* FIXME properly handle first level != 0 */
rstate->states[R600_PS_RESOURCE__RESOURCE0_WORD0] =
bo[1] = radeon_ws_bo_incref(rscreen->rw, tmp->uncompressed);
#endif
}
- pitch = (tmp->pitch[0] / tmp->bpt);
- pitch = (pitch + 0x7) & ~0x7;
+ pitch = align(tmp->pitch[0] / tmp->bpt, 8);
/* FIXME properly handle first level != 0 */
r600_pipe_state_add_reg(rstate, R600_GROUP_RESOURCE, R_038000_RESOURCE0_WORD0,