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diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index ea3dd901826a509d7b64e682ca0921434a9cf99b..41593b5c2c3b04330aae1479cab5e6163ec1a170 100644 (file)
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -179,6 +179,17 @@ src spec for RA is also used for the same RA as a dest.
 
 Mode is an augmentation of SV behaviour.  Some of these alterations are element-based (saturation), others involve post-analysis (predicate result) and others are Vector-based (mapreduce, fail-on-first).
 
+These are the modes:
+
+
+
+* **normal** mode is straight vectorisation.  no augmentations: the vector comprises an array of independently created results.
+* **ffirst** or data-dependent fail-on-first: see separate section.  the vector may be truncated depending on certain criterial.
+* **sat mode** or saturation: clamps each elemrnt result to a min/max rather than overflows / wraps.  allows signed and unsigned clamping.
+* **reduce mode**.  when M=1 a mapreduce is performed.  the result is a scalar.  a vector however is required, as it may be used to store intermediary computations.  the result is in the first element with a nonzero predicate bit.
+  note that reduce mode only applies to 2 src operations.
+* **pred-result** will test the result (CR testing selects a bit of CR and inverts it, just like branch testing) and if the test fails it is as if the predicate bit was zero.  When Rc=1 the CR element (CR0) however is still stored in the CR regfile.  This scheme does not apply to crops (crand, cror).
+
 | 0-1 |  2  |  3   4  |  description              |
 | --- | --- |---------|-------------------------- |
 | 00  |   0 |  sz  dz | normal mode              |
@@ -189,14 +200,10 @@ Mode is an augmentation of SV behaviour.  Some of these alterations are element-
 | 11  | inv | CR-bit  |  Rc=1: pred-result CR sel |
 | 11  | inv | sz   dz |  Rc=0: pred-result z/nonz |
 
-Mode types:
+Fields:
 
-* **sz dz predicate zeroing**  if predication is enabled will put zeros into the dest (or as src in the case of twin pred) when the predicate bit is zero.  otherwise the element is ignored or skipped, depending on context.
-* **ffirst** or data-dependent fail-on-first: see separate section.
-* **sat mode** or saturation: clamps the result to a min/max rather than overflows / wraps.  allows signed and unsigned clamping.
-* **reduce mode**.  when M=1 a mapreduce is performed.  the result is a scalar.  a vector however is required, as it may be used to store intermediary computations.  the result is in the first element with a nonzero predicate bit.
-  note that reduce mode only applies to 2 src operations.
-* **pred-result** will test the result (CR testing selects a bit of CR and inverts it, just like branch testing) and if the test fails it is as if the predicate bit was zero.  When Rc=1 the CR element (CR0) however is still stored in the CR regfile.  This scheme does not apply to crops (crand, cror).
+* **sz / dz**  if predication is enabled will put zeros into the dest (or as src in the case of twin pred) when the predicate bit is zero.  otherwise the element is ignored or skipped, depending on context.
+* **inv CR bit** just as in branches (BO) these bits allow testing of a CR bit and whether it is set (inv=0) or unset (inv=1)
 
 ## Notes about rounding, clamp and saturate