size = Param.Int("TLB size")
class MipsDTB(MipsTLB):
- type = 'DTB'
+ type = 'MipsDTB'
cxx_namespace = 'MipsISA'
cxx_class = 'DTB'
size = 64
class MipsITB(MipsTLB):
- type = 'ITB'
+ type = 'MipsITB'
cxx_namespace = 'MipsISA'
cxx_class = 'ITB'
size = 64
class MipsUTB(MipsTLB):
- type = 'UTB'
+ type = 'MipsUTB'
cxx_namespace = 'MipsISA'
cxx_class = 'UTB'
size = 64
FaultVect AlignmentFault::_vect = 0x0301;
FaultStat AlignmentFault::_count;
-FaultName ResetFault::_name = "reset";
+FaultName ResetFault::_name = "Reset Fault";
#if FULL_SYSTEM
FaultVect ResetFault::_vect = 0xBFC00000;
#else
FaultVect SystemCallFault::_vect = 0x0180;
FaultStat SystemCallFault::_count;
-FaultName CoprocessorUnusableFault::_name = "Coprocessor Unusable";
+FaultName CoprocessorUnusableFault::_name = "Coprocessor Unusable Fault";
FaultVect CoprocessorUnusableFault::_vect = 0x180;
FaultStat CoprocessorUnusableFault::_count;
-FaultName ReservedInstructionFault::_name = "Reserved Instruction";
+FaultName ReservedInstructionFault::_name = "Reserved Instruction Fault";
FaultVect ReservedInstructionFault::_vect = 0x0180;
FaultStat ReservedInstructionFault::_count;
-FaultName ThreadFault::_name = "thread";
+FaultName ThreadFault::_name = "Thread Fault";
FaultVect ThreadFault::_vect = 0x00F1;
FaultStat ThreadFault::_count;
void ResetFault::invoke(ThreadContext *tc)
{
+#if FULL_SYSTEM
DPRINTF(MipsPRA,"%s encountered.\n", name());
/* All reset activity must be invoked from here */
tc->setPC(vect());
tc->setNextPC(vect()+sizeof(MachInst));
tc->setNextNPC(vect()+sizeof(MachInst)+sizeof(MachInst));
DPRINTF(MipsPRA,"(%x) - ResetFault::invoke : PC set to %x",(unsigned)tc,(unsigned)tc->readPC());
+#endif
+
+ // Set Coprocessor 1 (Floating Point) To Usable
+ tc->setMiscReg(MipsISA::Status, MipsISA::Status | 0x20000000);
}
void ReservedInstructionFault::invoke(ThreadContext *tc)
// warn("Status: %x, Cause: %x\n",tc->readMiscReg(MipsISA::Status),tc->readMiscReg(MipsISA::Cause));
#else
- panic("%s encountered.\n", name());
+ warn("%s (CP%d) encountered.\n", name(), coProcID);
#endif
}
/*
- * Copyright \eN) 2007 MIPS Technologies, Inc. All Rights Reserved
+ * Copyright (c) 2007 MIPS Technologies, Inc.
+ * All rights reserved.
*
- * This software is part of the M5 simulator.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
*
- * THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
- * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
- * TO THESE TERMS AND CONDITIONS.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * Permission is granted to use, copy, create derivative works and
- * distribute this software and such derivative works for any purpose,
- * so long as (1) the copyright notice above, this grant of permission,
- * and the disclaimer below appear in all copies and derivative works
- * made, (2) the copyright notice above is augmented as appropriate to
- * reflect the addition of any new copyrightable work in a derivative
- * work (e.g., Copyright
\eN) <Publication Year> Copyright Owner), and (3)
- * the name of MIPS Technologies, Inc. (\e$(B!H\e(BMIPS\e$(B!I\e(B) is not used in any
- * advertising or publicity pertaining to the use or distribution of
- * this software without specific, written prior authorization.
- *
- * THIS SOFTWARE IS PROVIDED \e$(B!H\e(BAS IS.\e$(B!I\e(B MIPS MAKES NO WARRANTIES AND
- * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
- * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
- * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
- * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
- * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
- * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
- * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
- * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
- * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
- * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
- *
- * Authors: Gabe M. Black
- * Korey L. Sewell
+ * Authors: Gabe Black
+ * Korey Sewell
* Jaidev Patwardhan
*/
output exec {{
bool isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num)
{
+#if !FULL_SYSTEM
+ return true;
+#else
MiscReg Stat = xc->readMiscReg(MipsISA::Status);
switch(cop_num)
{
case 0:
{
-#if FULL_SYSTEM
- MiscReg Dbg = xc->readMiscReg(MipsISA::Debug);
- if((Stat & 0x10000006) == 0 // EXL, ERL or CU0 set, CP0 accessible
- && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible
- && (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode
- // Unable to use Status_CU0, etc directly, using bitfields & masks
- return false;
- }
-#else
- //printf("Syscall Emulation Mode: CP0 Enable Check defaults to TRUE\n");
-#endif
+ MiscReg Dbg = xc->readMiscReg(MipsISA::Debug);
+ if((Stat & 0x10000006) == 0 // EXL, ERL or CU0 set, CP0 accessible
+ && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible
+ && (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode
+ // Unable to use Status_CU0, etc directly, using bitfields & masks
+ return false;
+ }
+
}
break;
case 1:
break;
}
return true;
+#endif
}
bool inline isCoprocessor0Enabled(%(CPU_exec_context)s *xc)
{
#include "base/str.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
+#include "sim/process.hh"
+#include "mem/page_table.hh"
#include "params/MipsDTB.hh"
#include "params/MipsITB.hh"
#include "params/MipsTLB.hh"
Fault
ITB::translate(RequestPtr &req, ThreadContext *tc)
{
+#if !FULL_SYSTEM
+ Process * p = tc->getProcessPtr();
+
+ Fault fault = p->pTable->translate(req);
+ if(fault != NoFault)
+ return fault;
+
+ return NoFault;
+#else
if(MipsISA::IsKSeg0(req->getVaddr()))
{
// Address will not be translated through TLB, set response, and go!
}
}
return checkCacheability(req);
+#endif
}
Fault
DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
{
+#if !FULL_SYSTEM
+ Process * p = tc->getProcessPtr();
+
+ Fault fault = p->pTable->translate(req);
+ if(fault != NoFault)
+ return fault;
+
+ return NoFault;
+#else
if(MipsISA::IsKSeg0(req->getVaddr()))
{
// Address will not be translated through TLB, set response, and go!
}
}
return checkCacheability(req);
+#endif
}
///////////////////////////////////////////////////////////////////////
#if !FULL_SYSTEM
void FaultBase::invoke(ThreadContext * tc)
{
- fatal("fault (%s) detected @ PC %p", name(), tc->readPC());
+ panic("fault (%s) detected @ PC %p", name(), tc->readPC());
}
#else
void FaultBase::invoke(ThreadContext * tc)
projects / gem5.git / commitdiff