panfrost/midgard: Copy prop for texture registers
authorAlyssa Rosenzweig <alyssa@rosenzweig.io>
Thu, 25 Apr 2019 04:08:46 +0000 (04:08 +0000)
committerAlyssa Rosenzweig <alyssa@rosenzweig.io>
Thu, 25 Apr 2019 20:37:45 +0000 (20:37 +0000)
We'll want to unify this with main copy prop (and extend to varyings),
but that'll take more care to handle some special cases, so leave it as
a stub pass for now.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
src/gallium/drivers/panfrost/midgard/midgard_compile.c

index b5ab103298e147984755c8ef0aa67af8d7abbd70..72455c7dc87022337c6b114b48b27b7fb7443afc 100644 (file)
@@ -1788,8 +1788,6 @@ emit_tex(compiler_context *ctx, nir_tex_instr *instr)
                                 emit_mir_instruction(ctx, ins);
                         }
 
-                        //midgard_pin_output(ctx, index, REGISTER_TEXTURE_BASE + in_reg);
-
                         break;
                 }
 
@@ -3220,6 +3218,40 @@ midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block)
         return progress;
 }
 
+static bool
+midgard_opt_copy_prop_tex(compiler_context *ctx, midgard_block *block)
+{
+        bool progress = false;
+
+        mir_foreach_instr_in_block_safe(block, ins) {
+                if (ins->type != TAG_ALU_4) continue;
+                if (!OP_IS_MOVE(ins->alu.op)) continue;
+
+                unsigned from = ins->ssa_args.src1;
+                unsigned to = ins->ssa_args.dest;
+
+                /* Make sure it's a familiar type of special move. Basically we
+                 * just handle the special dummy moves emitted by the texture
+                 * pipeline. TODO: verify. TODO: why does this break varyings?
+                 */
+
+                if (from >= SSA_FIXED_MINIMUM) continue;
+                if (to < SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE)) continue;
+                if (to > SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE + 1)) continue;
+
+                mir_foreach_instr_in_block_from_rev(block, v, mir_prev_op(ins)) {
+                        if (v->ssa_args.dest == from) {
+                                v->ssa_args.dest = to;
+                                progress = true;
+                        }
+                }
+
+                mir_remove_instruction(ins);
+        }
+
+        return progress;
+}
+
 /* The following passes reorder MIR instructions to enable better scheduling */
 
 static void
@@ -3769,6 +3801,7 @@ midgard_compile_shader_nir(nir_shader *nir, midgard_program *program, bool is_bl
 
                 mir_foreach_block(ctx, block) {
                         progress |= midgard_opt_copy_prop(ctx, block);
+                        progress |= midgard_opt_copy_prop_tex(ctx, block);
                         progress |= midgard_opt_dead_code_eliminate(ctx, block);
                 }
         } while (progress);