Added bmask, pywriter failing

diff --git a/openpower/isa/av.mdwn b/openpower/isa/av.mdwn
index 94937abb0f00782ce7fd2b349811048e97547fe2..7bd3738c977b9e46fdbab5633fab111b3a1d4d04 100644 (file)
--- a/openpower/isa/av.mdwn
+++ b/openpower/isa/av.mdwn
@@ -169,3 +169,33 @@ Pseudo-code:
 Special Registers Altered:
 
     CR0                    (if Rc=1)
+
+# DRAFT bmask (don't know full name)
+ 
+BM2-Form
+ 
+* bmask  RT,RA,RB,mode
+
+Pseudo-code:
+
+    if _RB = 0 then mask <- [1] * XLEN else mask = (RB)
+    a1 <- (RA) & mask
+    if mode[1] then a1 <- ¬ra
+    mode2 <- mode[2:3]
+    if mode2 = 0 then a2 <- (¬ra)+1
+    if mode2 = 1 then a2 <- ra-1
+    if mode2 = 2 then a2 <- ra+1
+    if mode2 = 3 then a2 <- ¬(ra+1)
+    a1 <- a1 & mask
+    a2 <- a2 & mask
+    # select operator
+    mode3 <- mode[3:4]
+    if mode3 = 0 then result <- a1 | a2
+    if mode3 = 1 then result <- a1 & a2
+    if mode3 = 2 then result <- a1 ^ a2
+    if mode3 = 3 then result <- UNDEFINED
+    result <- result & mask
+    # optionally restore masked-out bits
+    if L = 1 then
+        result <- result | (RA & ¬mask)
+    RT <- result

diff --git a/openpower/isatables/minor_22.csv b/openpower/isatables/minor_22.csv
index 971560617c416b9eff797b2133d02f4b464ce36d..f23ff1ddb93aac46e45325a3658c3f73bcfb0192 100644 (file)
--- a/openpower/isatables/minor_22.csv
+++ b/openpower/isatables/minor_22.csv
@@ -17,3 +17,4 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 0111110110-,ALU,OP_ABSADD,RA,RB,RT,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,absdacs,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 # Vector bitmanip
 0110001110-,ALU,OP_CPROP,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,cprop,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+------10001,ALU,OP_BMASK,RA,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,cprop,BM2,,1,unofficial until submitted and approved/renumbered by the opf isa wg

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 275be81fb1c86afc3612bb12662f3777a91f72f2..941a89f0bb2eedfc323b3a51c52464bd8cbd03ef 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1299,6 +1299,11 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
             illegal = False
             ins_name = asmop
 
+        # and anything bmask
+        if asmop.startswith('bmask'):
+            illegal = False
+            ins_name = asmop
+
         # and anything ternlog
         if asmop.startswith('ternlog'):
             illegal = False

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index 5b9c888a25f9e8a1d888f856a11d6e94eae8c9df..f15cb4998ae561e9f3b68837864e8180d15f9544 100644 (file)
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -455,6 +455,7 @@ class MicrOp(Enum):
     OP_ABSDIFF = 91
     OP_ABSADD = 92
     OP_CPROP = 93
+    OP_BMASK = 94
 
 
 @unique

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index 0c4b24e973e0fb356ebfec071fe7647028f2541e..85b0fe3bbb4cac64a76f08331b59376bc47006eb 100644 (file)
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -334,6 +334,20 @@ class SVP64Asm:
         # they can - if implementations then choose - be Vectorised
         # (sv.fsins) because they are general-purpose scalar instructions
 
+        # 1.6.2.1 BM-FORM
+        #   |0     |6    |10  |15  |22  |23    |31|
+        #   | PO   |  RS | me | sh | me |   XO |Rc|
+        if opcode == ('bmask'):
+            fields = list(map(int, fields))
+            insn = 59 << (31-5)  # opcode 59, bits 0-5
+            insn |= fields[0] << (31-10)  # RT       , bits 6-10
+            insn |= fields[1] << (31-20)  # RB       , bits 16-20
+            insn |= 0b1000001110 << (31-30)  # XO       , bits 21..30
+            log("fsins", bin(insn))
+            yield ".long 0x%x" % insn
+            return
+
+
         # and fsins
         # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
         # however we are out of space with opcode 22