Preserve 'signed'-ness of a verilog wire through RTLIL

As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987, now:

RTLIL::wire holds an is_signed field.
This is exported in JSON backend
This is exported via dump_rtlil command
This is read in via ilang_parser

diff --git a/backends/ilang/ilang_backend.cc b/backends/ilang/ilang_backend.cc
index 6e3882d2d02f91fc30ad2cbdd5c5cafc71ebe418..3a418de3c963766b85826660398717472cbac168 100644 (file)
--- a/backends/ilang/ilang_backend.cc
+++ b/backends/ilang/ilang_backend.cc
@@ -131,6 +131,8 @@ void ILANG_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::
                f << stringf("output %d ", wire->port_id);
        if (wire->port_input && wire->port_output)
                f << stringf("inout %d ", wire->port_id);
+       if (wire->is_signed)
+               f << stringf("signed ");
        f << stringf("%s\n", wire->name.c_str());
 }
 

diff --git a/backends/json/json.cc b/backends/json/json.cc
index 1a8b757ef1f1fdb95b53f6fe16a0aee5d65d5909..5edc50f609e3edd2e630697001968e752afc2963 100644 (file)
--- a/backends/json/json.cc
+++ b/backends/json/json.cc
@@ -160,6 +160,8 @@ struct JsonWriter
                                f << stringf("          \"offset\": %d,\n", w->start_offset);
                        if (w->upto)
                                f << stringf("          \"upto\": 1,\n");
+                       if (w->is_signed)
+                               f << stringf("          \"signed\": %d,\n", w->is_signed);
                        f << stringf("          \"bits\": %s\n", get_bits(w).c_str());
                        f << stringf("        }");
                        first = false;
@@ -227,6 +229,8 @@ struct JsonWriter
                                f << stringf("          \"offset\": %d,\n", w->start_offset);
                        if (w->upto)
                                f << stringf("          \"upto\": 1,\n");
+                       if (w->is_signed)
+                               f << stringf("          \"signed\": %d,\n", w->is_signed);
                        f << stringf("          \"attributes\": {");
                        write_parameters(w->attributes);
                        f << stringf("\n          }\n");

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index d35335747e4c5e7fb02380849ae7eb261d7153b0..93fcfb3969d706488e2a9b07976e4a4ad1c11eca 100644 (file)
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -1058,6 +1058,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
                        wire->port_input = is_input;
                        wire->port_output = is_output;
                        wire->upto = range_swapped;
+                       wire->is_signed = is_signed;
 
                        for (auto &attr : attributes) {
                                if (attr.second->type != AST_CONSTANT)

diff --git a/frontends/ilang/ilang_parser.y b/frontends/ilang/ilang_parser.y
index 8e21fb176a82db8f5e0833fbe785b273f3c9b27d..43b628e095ec6dc97faf293fab425b6018363cfa 100644 (file)
--- a/frontends/ilang/ilang_parser.y
+++ b/frontends/ilang/ilang_parser.y
@@ -192,6 +192,9 @@ wire_options:
        wire_options TOK_UPTO {
                current_wire->upto = true;
        } |
+       wire_options TOK_SIGNED {
+               current_wire->is_signed = true;
+       } |
        wire_options TOK_OFFSET TOK_INT {
                current_wire->start_offset = $3;
        } |

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 196e301b6c04e20fd449f197cf0cafd96467f230..98d6ed41fd53dc75fbbc9e0dc2ca33ed2223b6d5 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1862,6 +1862,7 @@ RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *oth
        wire->port_input = other->port_input;
        wire->port_output = other->port_output;
        wire->upto = other->upto;
+       wire->is_signed = other->is_signed;
        wire->attributes = other->attributes;
        return wire;
 }
@@ -2445,6 +2446,7 @@ RTLIL::Wire::Wire()
        port_input = false;
        port_output = false;
        upto = false;
+       is_signed = false;
 
 #ifdef WITH_PYTHON
        RTLIL::Wire::get_all_wires()->insert(std::pair<unsigned int, RTLIL::Wire*>(hashidx_, this));

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 11c45bbec77904615e85d669cfd5b2a181fb1bcb..04d4325d1de55da1d4869cbf4f4352e930d0865d 100644 (file)
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -1353,7 +1353,7 @@ public:
        RTLIL::Module *module;
        RTLIL::IdString name;
        int width, start_offset, port_id;
-       bool port_input, port_output, upto;
+       bool port_input, port_output, upto, is_signed;
 
 #ifdef WITH_PYTHON
        static std::map<unsigned int, RTLIL::Wire*> *get_all_wires(void);