radeonsi: disable perfect ZPASS counts for PIPE_QUERY_OCCLUSION_PREDICATE

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
index 381ad21a4e34955e0d02d7453fbdf79f88f13569..062c3193947b35148955470b41520dd9fd2d887a 100644 (file)
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -425,8 +425,9 @@ struct r600_common_context {
        unsigned flags; /* flush flags */
 
        /* Queries. */
-       /* The list of active queries. Only one query of each type can be active. */
+       /* The list of active queries. */
        int                             num_occlusion_queries;
+       int                             num_perfect_occlusion_queries;
        /* Keep track of non-timer queries, because they should be suspended
         * during context flushing.
         * The timer queries (TIME_ELAPSED) shouldn't be suspended for blits,

diff --git a/src/gallium/drivers/radeon/r600_query.c b/src/gallium/drivers/radeon/r600_query.c
index f9a5721fb9762dd62af4a31acd60a85689f0b3f4..7a2d2ee7f316d7e6b9a7e1ea08305fdec882f9fc 100644 (file)
--- a/src/gallium/drivers/radeon/r600_query.c
+++ b/src/gallium/drivers/radeon/r600_query.c
@@ -414,14 +414,22 @@ static void r600_update_occlusion_query_state(struct r600_common_context *rctx,
        if (type == PIPE_QUERY_OCCLUSION_COUNTER ||
            type == PIPE_QUERY_OCCLUSION_PREDICATE) {
                bool old_enable = rctx->num_occlusion_queries != 0;
-               bool enable;
+               bool old_perfect_enable =
+                       rctx->num_perfect_occlusion_queries != 0;
+               bool enable, perfect_enable;
 
                rctx->num_occlusion_queries += diff;
                assert(rctx->num_occlusion_queries >= 0);
 
+               if (type == PIPE_QUERY_OCCLUSION_COUNTER) {
+                       rctx->num_perfect_occlusion_queries += diff;
+                       assert(rctx->num_perfect_occlusion_queries >= 0);
+               }
+
                enable = rctx->num_occlusion_queries != 0;
+               perfect_enable = rctx->num_perfect_occlusion_queries != 0;
 
-               if (enable != old_enable) {
+               if (enable != old_enable || perfect_enable != old_perfect_enable) {
                        rctx->set_occlusion_query_state(&rctx->b, enable);
                }
        }

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index f559c73f065da6ecb3ea474b0103a47af396b5a9..057458c843a9b433d09ff09b2fd1ddd9c603ef43 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1310,16 +1310,18 @@ static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *s
 
        /* DB_COUNT_CONTROL (occlusion queries) */
        if (sctx->b.num_occlusion_queries > 0) {
+               bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
+
                if (sctx->b.chip_class >= CIK) {
                        radeon_emit(cs,
-                                   S_028004_PERFECT_ZPASS_COUNTS(1) |
+                                   S_028004_PERFECT_ZPASS_COUNTS(perfect) |
                                    S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
                                    S_028004_ZPASS_ENABLE(1) |
                                    S_028004_SLICE_EVEN_ENABLE(1) |
                                    S_028004_SLICE_ODD_ENABLE(1));
                } else {
                        radeon_emit(cs,
-                                   S_028004_PERFECT_ZPASS_COUNTS(1) |
+                                   S_028004_PERFECT_ZPASS_COUNTS(perfect) |
                                    S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
                }
        } else {